JEDEC publishes DDR5 SDRAM standard update: speeds, features, timings

JEDEC announced the publication of the DDR5 SDRAM standard update which included new features to enhance reliability and performance across a wide range of applications, in systems and high-performance servers.

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The new features for DDR5 memory from JEDEC include bounded fault error-correction support, Soft Post-Package Repair (sPPR) undo and lock, Memory Built-In Self-Test Post Package Repair (MBIST and mPPR), Adaptive RFM, and an MR4 extension.

JEDEC also expanded the timing definition and transfer speed of DDR5, ramping up to 6400 MT/s for DRAM core timings and 5600 MT/s for IO AC timings to help the industry build an ecosystem up to 5600 MT/s. JEDEC Chairman Mian Quddus explains: "The fact that this update to DDR5 is being published so soon after the initial launch of DDR5 in July 2020 underscores JEDEC's ongoing commitment to continual improvement, and represents a collective effort on the part of all involved member companies to better serve the industry".

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Joe Macri, Chief Technology Officer, Compute and Graphics Business Unit, AMD said: "AMD is proud of our ongoing collaboration with JEDEC, driving the high-performance computing industry forward with powerful improvements to DDR5 features. With the new JESD79-5A DDR5 standard, JEDEC offers the most advanced memory for high performance and reliability and continues our joint commitment to enabling the best possible experiences for end users".

Carolyn Duran, VP - Data Platforms Group, GM - Memory and IO Technologies at Intel said: "Close collaboration is required to deliver the system-level reliability and scale-up performance that data-centric workloads demand from DDR5. Micron is proud to work with JEDEC and a broad ecosystem to advance memory standards that empower customers to turn their data into insights faster".

Frank Ross, lead architect at Micron said: "Samsung is proud to see that DDR5 memory will be able to reach new heights in operating efficiency and self-correcting capabilities, something that we and other industry leaders have been working intently to standardize over the past 14 months. With these enhancements, the industry is setting an extremely firm foundation for one of the most ambitious memory upgrades ever ― an advancement particularly important for large server systems".

Young-Soo Sohn, vice president of the DRAM Memory Planning/Enabling Group at Samsung Electronics said: "As new reliability features have now become part of the DDR5 standard, SK hynix is pleased to be able to provide a more robust memory solution to our customers. Furthermore, being able to deliver higher device speeds will bring the overall system performance to the next levels. SK hynix has been providing DDR5 DIMM samples to the industry since 2019 for ecosystem readiness, and will continue to actively participate in future JEDEC activities for continued open innovation and ecosystem enabling".