IBM announces world's first sub-1 nanometer chip with nanostack technology doubling transistor density

IBM has announced what it calls the world's first sub-1 nanometer chip technology, unveiling a new 0.7nm process built around an entirely new transistor architecture called nanostack. The result is a chip the size of a human fingernail that packs nearly 100 billion transistors, almost double the density of IBM's previous 2nm chip from 2021.

IBM says the architecture could deliver either 50% higher performance or 70% greater energy efficiency compared to its predecessor, and it represents what the company believes is a viable path for chip scaling for at least the next decade. Before going ahead, it is worth clarifying what "sub-1 nanometer" actually means here.

Modern process node names have not corresponded to literal physical dimensions for decades. IBM's 0.7nm designation, which it also calls the 7 angstrom node, refers to a generation of manufacturing capability rather than a physical transistor size. What matters practically is that the architecture delivers the density and efficiency improvements that such a node implies.

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The nanostack architecture builds on IBM's existing nanosheet transistor technology, which it introduced with its 2nm chip in 2021 and which has since been adopted by TSMC, Samsung, and other leading foundries as the foundation for their own advanced nodes.

Rather than continuing to shrink transistors horizontally, nanostack stacks and staggers transistors vertically in a three-dimensional layout. Each transistor consists of three nanosheet elements, approximately five nanometers thick with nine nanometers between each layer, and each nanosheet is made up of roughly 15 rows of silicon atoms.

IBM also says the architecture allows different material combinations within stacked layers, potentially letting engineers optimize individual layers independently for performance, power, or other characteristics. IBM researchers demonstrated a 40% improvement in SRAM scaling using the nanostack architecture, the largest such improvement in roughly a decade.

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Between the 3nm and 2nm generations, SRAM scaling improved by only a few percent. The jump matters because SRAM is used for processor cache, and AI workloads are increasingly constrained by memory bandwidth and efficiency. Jay Gambetta, director of IBM Research, said the SRAM result will eventually be industrialized for AI workflows that require higher bandwidth and efficiency.

With our new nanostack architecture, we're not just making smaller transistors," Gambetta said. "We're reinventing how chips are built to deliver dramatically more power and energy efficiency.

IBM estimates nanostack chips could enter production within five years, though the company has not named specific manufacturing partners. Its previous nanosheet technology is being commercialized by Rapidus in Japan, which is targeting production of 2nm chips at scale by the second half of 2027. IBM has said it will share more details on commercialization plans in the future.