University of Illinois researchers found a way to stack silicon chip layers vertically with near-perfect yields

For roughly six decades, the semiconductor industry has followed a simple and reliable formula: make transistors smaller, pack more of them onto a chip, and watch performance climb. That formula, commonly known as Moore's Law, is now running into hard physical limits. A research team at the University of Illinois Urbana-Champaign thinks the next gains will come not from going smaller, but from going vertical.

Led by materials science and engineering professor Qing Cao, the team has developed a method for stacking multiple active layers of silicon circuits directly on top of one another on a single chip, achieving device yields between 98% and 100%. The results were published in Nature.

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Building high-performance silicon circuits typically requires temperatures approaching 1,000 degrees Celsius. Once the team installs the first layer of circuitry and metal wiring, they must keep any subsequent layers below 400 degrees to avoid damaging what is already in place. Previous attempts to work around this used alternative materials for the upper layers, but those devices consistently underperformed compared with standard silicon transistors.

Cao's team kept single-crystalline silicon and changed the method of adding it. They create ultrathin freestanding silicon nanomembranes, just 10 nanometers thick, from a donor wafer. The team then transfers these membranes onto the processed substrate using a roll laminator at temperatures no higher than 200 degrees Celsius. Because the membranes are so thin, they are flexible enough to conform to the surface beneath them, reducing the gaps and voids that typically form when engineers try to bond two rigid wafers.

The team also redesigned the transistor architecture to avoid high-temperature doping steps. Instead of conventional transistors, they used junctionless transistors, in which the silicon is uniformly and heavily doped before the stacking process begins. The ultrathin films still allow effective gate control, and the high doping levels keep contact resistance in check.

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Using this process, the researchers built three stacked layers, each containing 625 transistors, and connected them by vertical metal interconnects. The output current densities matched those of conventional silicon transistors produced at much higher temperatures and outperformed monolithic devices built from alternative materials by a factor of 3 to 4. The team used the stack to implement three-dimensional logic circuits and static random-access memory cells.

SRAM is a good example of this concept. Traditionally, a standard SRAM cell uses six transistors arranged on a flat plane to store a single bit of information. Distributing those transistors across multiple vertical layers achieves the same functionality in a much smaller footprint while shortening the communication paths between components.

The project has industry backing from IBM, Intel, and TSMC through Illinois Grainger Engineering's Center for Advanced Semiconductor Chips with Accelerated Performance. The team is now preparing to transfer the process to an industrial semiconductor foundry, an important step toward bringing monolithic 3D silicon chips out of the lab and into commercial production.