Leaked AMD Zen 6 EPYC Venice samples spotted with 64-192 cores across 1P & 2P setups on Congo, Kenya, and Nigeria Platforms

A series of new next-gen Zen 6 server EPYC processors from AMD have debuted on the open-source benchmarking platform OpenBenchmarking, thanks to Olrak29_ at X (formerly Twitter). These appear to be the first public sightings of the upcoming silicon, though performance is not indicative of the final result, as we're still dealing with early silicon. Codenamed 'Venice', AMD is on track to launch these 6th Gen EPYC processors in the second half of 2026.

Last April, AMD officially unveiled the codename and some architectural details for its next-generation EPYC family. The EPYC 9006 family is designed with the Zen 6 architecture and fabricated using TSMC's 2nm process. Current leaks underpin improved core counts, greater cache, and enhanced I/O capabilities, thanks to the new design and the higher density offered by the updated process node.

If we're to believe leaks, each Zen 6 CCD is moving from the standard 8-core structure to 12 cores, with 48MB of L3 cache, up from 32MB. The dense Zen 6c variant sees an even bigger jump from 16 cores to 32 cores per CCD, accompanied by 128MB of L3 cache (up from 32MB). This means that for a fully decked-out chip with eight Zen 6c CCDs, we're looking at 256 cores and 1GB of L3 cache. While industry insiders have teased this flagship spec, current data suggests the standard Zen 6 counterpart may top out at 96 cores with a similar eight CCD layout, unlike sixteen CCDs with Turin.

With that in mind, let's start analyzing today's leak. A series of chips has been tested across different platforms: Congo, Kenya, and Nigeria. These appear to be internal codenames for testing motherboards and systems supplied to partners for testing and validation. We'll analyze these chips platform-by-platform. Notably, all platforms are based on the SP7 socket, according to the leaker.

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The standout entry on the Congo platform is an engineering sample (100-000001053-03) with 192 cores / 384 threads clocked at 4.02 GHz. Early analysis suggests this is an 8 CCD + 2 IOD design. With 192 cores spread across 8 CCDs, we are looking at 24 cores per CCD. This strongly suggests this is a binned version of the standard 32-core Zen 6c CCD, with 8 cores disabled per CCD to optimize yields or power efficiency.

Kenya appears to be a testing ground for more traditional core counts. Here we find a 64-core sample (100-000001863-02) at 3.52 GHz and a 128-core counterpart (100-000001056-09), likely employing four full-fat 32-core Zen 6c CCDs.

The Nigeria platform focuses on 2P (dual-socket) configurations. The most notable entry here is the 192-core sample (100-000001051-08), doubling to 384 cores across the platform. Other mentions include a 128-core variant (100-000001056-03) and a 64-core model (100-000002138-02).

Apart from these increases in core counts and cache, the most notable change is the switch to a dual IOD setup. While EPYC has used a single central IOD since Zen 2, the shift to 16-channel DDR5 and PCIe Gen 6.0 requires more silicon real estate for memory controllers and high-speed interconnectivity. This is especially important, since AMD is promising 2x the CPU-to-GPU bandwidth and 1.6 TB/s of memory bandwidth with Venice. The move towards a dual IOD layout allows AMD to potentially dedicate one die to memory/Infinity Fabric and the other to high-speed I/O (PCIe/CXL). We expect AMD to share more concrete details at Computex this June.