AMD's next-gen EPYC 9755 'Turin' CPU spotted: 128C/256T Zen 5 up to 4.1GHz, with 650MB cache

AMD's next-generation EPYC 9755 "Turin" CPU with 128 cores and 256 threads of Zen 5 processing power being tested in ES (engineering sample) form.

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The leaks from the new Zen 5-powered EPYC 9755 processor with 128 cores and 256 threads with a base 2.70GHz CPU clock, and up to 4.10GHz boost clock speeds. These clock speeds might not be final, so we could expect a slight boost in base and boost clocks on the EPYC 9755 "Turin" CPU.

AMD's new EPYC 9755 "Turin" CPU also has a huge pool of cache: 512MB of L3 cache, 128MB of L2 cache, and 10MB of L1 cache for a total of 650MB of cache. The current EPYC 9654 CPU has only 384MB of L3 cache and 96MB of L2 cache. Another note is that AMD's new EPYC "Turin" Zen 5 CPUs have up to 16 x CCDs while "Zen 5c" SKUs have 8 CCDs. This means each CCD has 8 cores (16 x 8) and each CCD also features 4MB of L3 cache.

In this test, there were dual AMD EPYC 9755 "Turin" processors for a total of 256 cores and 512 threads with up to (an incredible) 1GB of L3 cache, 256MB of L2 cache, and 20MB of L1 cache for a combined total of 1276MB of cache. That is a 31% increase in cache over the Zen 4-based EPYC processors, and that stack of cache will only increase once 3D V-Cache "Turin-X" EPYC processors arrive.

Leaker HXL also teased the EPYC 9965 processor, based on the Zen 5c architecture with a total of 192 cores and 384 threads, with a 500W TDP. These are the two EPYC "Turin" SKUs that HXL leaked:

• EPYC 9755 "Zen 5" - 16 CCDs / 8 Cores Per CCD (128 Total) / 4 MB L3 Per Core (32 MB Per CCD) / 1 MB L2 Per Core (8 MB Per CCD) / 80 KB L1 Per Core (640 KB Per CCD) / 512 MB L3 + 128 MB L2 + 10 MB L1 = 650 MB Cache
• EPYC 9654 "Zen 4"- 12 CCDs/ 8 Cores Per CCD (96 Total) / 4 MB L3 Per Core (32 MB Per CCD) / 1 MB L2 Per Core (8 MB Per CCD) / 64 KB L1 Per Core (512 KB Per CCD) / 384 MB L3 + 96 MB L2 + 6 MB L1 = 496 MB Cache

AMD will unleash its new EPYC "Turin" CPUs later this year.