Recent reports claim that Intel hasn't been sharing the hot and juicy details with tech company heavy weights such as AMD and NVIDIA.
Among other things, the blog post mentioned that the USB 3.0 specification is not owned by Intel and that the giant chip maker is merely a part of the USB 3.0 Promoter Group (which includes other giants such as HP, MSFT, NEC, NXP, and TI).
Rumour 2: Intel is holding back the specification, and not sharing with the industry.
No Intel isn't holding back the specification, the whole point of Intel investing heavily (gazillions of dollars and bazillions of man hours) into creating this 'Dummies Guide' is to enable the industry to start building USB 3.0 into their silicon as soon as possible, so why would Intel purposefully delay? One danger however of distributing an unfinished spec is the risk of incompatible hardware down the line, leading to a right mess. As an Intel specification Intel has the responsibility to insure that specifications we deliver to the industry are fully developed and mature enough for others to use. The Intel host controller spec is expected to be unveiled to the industry as soon as possible, in the second half of the year. The impatience of our fellow chipset-makers (as described in the press) to leverage Intel's investment and begin to design great USB 3.0 supporting devices of their own is however very encouraging and should aid a fast USB 3.0 adoption ramp.
Could anyone invest the necessary time and money to create such a host controller specification? Of course they could - but with Intel's Industry stewardship in sharing our spec the industry doesn't have to make the additional time and resource commitment.
USB 3.0 is slated to be officially launched sometime this year with consumer products ready for sale in 2009 or a little later. During the 2007 Intel Developer Forum, Pat Gelsinger demonstrated USB 3.0 and said that it is targeted at ten times the current bandwidth of USB 2.0 Hi-Speed (or about 4.8 Gbit per second) by utilizing two additional high-speed differential pairs for "Superspeed" mode.