Intel has come out swinging in a big way celebrating the 75th anniversary of the transistor, where at IEDM 2022 (the International Electron Devices Meeting) that the company is aiming for 10x density improvements in packaging technology, using a novel material that is just 3 atoms thick in order to advance transistor scaling.
Intel has unveiled its latest research breakthroughs that are fueling the innovation pipeline in order to keep Moore's Law on track towards 1 trillion transistors by the year 2030, where at the IEDM 2022 conference, Intel researchers showed off the latest advancements in 3D packaging technology.
The researchers showcased a huge 10x improvement in density, using novel materials for 2D transistor scaling beyond RibbonFET, including a super-thin material that is just 3 atoms thick. This will pave the way for massive improvements in energy efficiency and memory for higher-performing computing, as well as more advancements in the world of quantum computing.
Gary Patton, Intel vice president and general manager of Components Research and Design Enablement explains: "Seventy-five years since the invention of the transistor, innovation driving Moore's Law continues to address the world's exponentially increasing demand for computing. At IEDM 2022, Intel is showcasing both the forward-thinking and concrete research advancements needed to break through current and future barriers, deliver to this insatiable demand, and keep Moore's Law alive and well for years to come".
To celebrate the milestone of the 75th anniversary of the transistor, Dr. Ann Kelleher, Intel executive vice president and general manager of Technology Development, will be leading a plenary session at IEDM 2022. There, Kelleher will outline the paths forward for continued industry innovation, pushing the ecosystem around a systems-based strategy to handle the world's continued demands on computing, and effectively innovate to advance at a Moore's Law pace.
The key innovations Intel is working on are pushing towards continued power, performance, and cost improvements over the last 20 years -- in line with Moore's Law -- something that includes including strained silicon, Hi-K metal gate and FinFET - in personal computers, graphics processors and data centers started with Intel's Components Research Group. Further research, including RibbonFET gate-all-around (GAA) transistors, PowerVia back side power delivery technology and packaging breakthroughs like EMIB and Foveros Direct, are on the roadmap today.
But at IEDM 2022, Intel's Components Research Group proudly showed its commitment to innovating across three key areas to continue Moore's Law. These areas are: new 3D hybrid bonding packaging technology to enable seamless integration of chiplets; super-thin, 2D materials to fit more transistors onto a single chip; and new possibilities in energy efficiency and memory for higher-performing computing.
Intel says that the journey to extend Moore's Law to 1 trillion transistors on a single package will include advanced packaging that is capable of an additional 10x interconnect density, which leads to quasi-monolithic chips, Intel's materials innovations have also identified practical design choices that are capable of meeting the requirements of transistor scaling using novel material that is just 3 atoms thick, which enable the company to continue scaling up to, and beyond RibbonFET.
Intel looks to super-thin '2D' materials to fit more transistors onto a single chip:
- Intel demonstrated a gate-all-around stacked nanosheet structure using 2D channel material just 3 atoms thick, while achieving near-ideal switching of transistors on a double-gate structure at room temperature with low leakage current. These are two key breakthroughs needed for stacking GAA transistors and moving beyond the fundamental limits of silicon.
- Researchers also revealed the first comprehensive analysis of electrical contact topologies to 2D materials that could further pave the way for high-performing and scalable transistor channels.
Intel brings new possibilities in energy efficiency and memory for higher-performing computing:
- To use chip area more effectively, Intel redefines scaling by developing memory that can be placed vertically above transistors. In an industry first, Intel demonstrates stacked ferroelectric capacitors that match the performance of conventional ferroelectric trench capacitors and can be used to build FeRAM on a logic die.
- An industry-first device-level model captures mixed phases and defects for improved ferroelectric hafnia devices, marking significant progress for Intel in supporting industry tools to develop novel memories and ferroelectric transistors.
- Bringing the world one step closer to transitioning beyond 5G and solving the challenges of power efficiency, Intel is building a viable path to 300 millimeter GaN-on-silicon wafers. Intel breakthroughs in this area demonstrate a 20 times gain over industry standard GaN and sets an industry record figure-of-merit for high performance power delivery.
- Intel is making breakthroughs on super-energy-efficient technologies, specifically transistors that don't forget, retaining data even when the power is off. Already, Intel researchers have broken two of three barriers keeping the technology from being fully viable and operational at room temperature.