JEDEC reveals new LPDDR6 memory standard: higher speeds for mobile devices and AI

JEDEC has just announced the publication of its new LPDDR6 memory standard dubbed "JESD209-6" which has been designed to boost memory speeds and efficiency, for the future of mobile devices and AI.

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The new LPDDR6 memory standard represents a significant advancement in memory technology, increasing performance, power efficiency, and security. In order to enable AI applications and other high-performance workloads, the new LPDDR6 standard uses a dual sub-channel architecture that allows for flexible operation while maintaining a small access granularity of 32 bytes.

Mian Quddus, JEDEC's Chairman of the Board of Directors, explains: "JEDEC is proud to introduce LPDDR6, the culmination of years of dedicated effort by members of the JC-42.6 Subcommittee for Low Power Memories. By delivering a balance of power efficiency, robust security options and high performance, LPDDR6 is an ideal choice for next-generation mobile devices, AI and related applications to thrive in a power-conscious, high-performance world".

LPDDR6 key features include:

High Performance

To enable AI applications and other high-performance workloads, LPDDR6 employs a dual sub-channel architecture that allows for flexible operation while maintaining a small access granularity of 32 bytes. In addition, LPDDR6 key features offer:

• 2 sub-channels per die, 12 data signal lines (DQs) per sub-channel to optimize channel performance capabilities
• Each sub-channel includes 4 command/address (CA) signals, optimized to reduce ball count and improve data access speed
• Static efficiency mode designed to support high-capacity memory configurations and maximize bank resource utilization
• Flexible data access, on-the-fly burst length control to support 32B & 64B access
• Dynamic write NT-ODT (non-target on-die termination) enables the memory to adjust ODT based on workload demands, improving signal integrity

Power Efficiency

To help meet ever-increasing demands for power efficiency, LPDDR6 operates with a lower voltage and low power consumption capable VDD2 supply as compared to LPDDR5, and mandates two supplies for VDD2. Additional power-saving features include:

• Alternating clock command inputs are used to enhance performance and efficiency
• Dynamic Voltage Frequency Scaling for Low power (DVFSL) lowers the VDD2 supply during low-frequency operation to reduce power consumption
• Dynamic Efficiency mode utilizes a single sub-channel interface for low-power, low-bandwidth use cases
• Support for both partial self and active refresh to reduce refresh power usage

Security and Reliability

Security and reliability improvements over the previous version of the standard include:

• Per Row Activation Counting (PRAC) to support DRAM data integrity
• Carve-out Meta mode is defined to enhance overall system reliability by allocating specific memory regions for critical tasks
• Support for programmable link protection scheme and on-die error correction code (ECC)
• Capable of supporting Command/Address (CA) parity, error scrubbing, and memory built-in self-test (MBIST) for enhanced error detection and system reliability