Check out this beautiful die shot of AMD's new Ryzen AI 300 'Strix Point' APU

AMD's new Ryzen AI 300 series "Strix Point" APUs are now out in the wild inside of a new wave of Copilot+ AI systems, and now we've got our first (and most beautiful) die shot of Strix Point. Check it out:

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The Zen 5-based Strix Point APU die is larger than the previous-gen Zen 4-based Phoenix APU, measuring 12.06 mm x 18.71 mm (L x W), compared to Phoenix's 9.06 mm x 15.01 mm. This is because AMD has a bigger CPU (Zen 5), a bigger integrated GPU (RDNA 3.5), and a bigger NPU (XDNA 2).

AMD also uses the improved TSMC N4P process node for the Strix Point APU at TSMC after using the N4 process node on its Phoenix and Hawk Point APUs. Nemez (GPUsAreMagic) annotated the die shot in fantastic detail, as seen in the image above.

AMD's new Strix Point APU has up to 12 cores spread across two CCXs. One features 4 x Zen 5 cores that share 16MB of L3 cache, and the other has 8 x Zen 5c cores sharing 8MB of L3 cache. The two CCX connect to the rest of the chip over Infinity Fabric, while the new RDNA 3.5-based integrated GPU takes up more of the central space of the die.

The new RDNA 3.5-based GPU has 8 workgroup processors (WGPs), or 16 Compute Units with 1024 stream processors. There are other components, including 4 render backends worth 16 ROPs and control logic. The RDNA 3.5 GPU has its own 2MB of L2 cache that cushions transfers to the Infinity Fabric.

• Read more: AMD Ryzen AI 300 series 'Strix Point' APU laptops launch: Zen 5 CPU, RDNA 3.5 GPU, XDNA 2 NPU
• Read more: AMD's new RDNA 3.5-based Radeon 890M, 880M integrated GPU inside Strix Point APUs tested

Strix Point has a second-generation XDNA 2-based NPU that is larger than the XDNA-based NPU in Phoenix, with 32 AI engine tiles, talking with its own high-speed local memory and a control logic that interfaces with Infinity Fabric. AMD is pushing the XDNA 2-based NPU inside of its Ryzen AI 300 series "Strix Point" APUs with 50 TOPS of AI workload performance.

Moving onto the memory controller of Strix Point, which supports dual-channel (160-bit) DDR5 at native DDR5-5600 and 128-bit LPDDR5-7500 memory. The memory controller sports an unknown amount of SRAM cache, with Nemez noting it was also seen on "Phoenix 2" and "Phoenix" dies, but not on the memory controller of the cIOD found on "Raphael" and "Dragon Range".