AMD has published a white paper making aggressive performance claims for its 6th Gen EPYC Venice server CPUs, directly targeting NVIDIA Vera.
In SPECrate 2026 Integer, AMD claims the 256-core EPYC 9996 delivers 2.24 times the platform-level performance of NVIDIA's 88-core Vera system and 1.2 times the per-core performance. At the rack level, modelled within a 100kW power budget, AMD puts the EPYC 9996 at 3.4 times the throughput of a Vera-based platform.
Popular Now: Xbox Series X can now run PS5 games thanks to a new emulator
Against Intel's Xeon 6980P, AMD's claims are similarly bold, with gains of 2.4x to 3.7x across enterprise workloads including server-side Java, OpenSSL, MongoDB, Redis, and NGINX, and up to 3.13x in HPC tasks like molecular dynamics and weather forecasting.
In terms of memory bandwidth numbers, EPYC Venice uses a 16-channel memory design supporting up to 12,800 MT/s RDIMM modules, delivering 1,298 GB/s of total bandwidth against Vera's 1,099 GB/s. That's an 18% advantage overall and 8% higher per-core bandwidth, despite Venice having more cores to feed.
Before treating any of this as settled, though, there are some configuration details worth flagging. Several of the Vera comparisons use a down-cored EPYC 9996 running 96 cores rather than the full 256, and AMD ran its Venice tests with GCC 16.1, while NVIDIA's Vera results in the white paper used GCC 15.2.
Different compiler versions can meaningfully affect benchmark outcomes, so comparing across them is not best practice. The rack-level figures are also modelled estimates based on a combination of benchmark data and system-level assumptions rather than measurements from physical racks running both chips side by side. AMD has also revised its methodology since the earlier June analysis, incorporating SPECrate 2026 instead of SPECrate 2017, which makes direct comparisons to its earlier numbers tricky.
Frequently Asked Questions
Open a question for an answer from TweakTown's coverage of this news, or ask your own below.
How did AMD configure the down-cored 96-core EPYC 9996 in the Vera comparisons?
What impact could GCC 16.1 versus GCC 15.2 have on the SPECrate 2026 results?
How was the 100kW rack-level throughput estimate for EPYC Venice modeled?
How does the 16-channel memory design on EPYC Venice translate into real server bandwidth benefits?
Have a question that isn't listed here? Ask below, and TweakBot will answer it.
None of that means the results are wrong. It means they are AMD's numbers, built around AMD's methodology, and the only answer that will actually matter is what independent reviewers find when they get both chips on the same test bench under the same conditions.
