AMD's 256-core EPYC Venice die shot has been spotted on Moscone Center banners ahead of Lisa Su's keynote

Q: What is the core and thread count configuration confirmed by the Venice die shot banners?

The die shot banners confirm eight compute dies (CCDs) each with 32 Zen 6c cores, for a total of 256 cores across the package. That flagship configuration provides 512 threads.

Q: What manufacturing process is Venice produced on and what transistor technology does it use?

Venice is in volume production on TSMC's 2nm process. That 2nm node transitions from FinFET to Nanosheet transistors.

Q: What performance and power improvements does AMD claim for Venice compared to EPYC Turin?

AMD says Venice delivers more than 70% improvement in performance and efficiency versus its current-generation EPYC Turin chips. It also promises a greater than 30% increase in thread density.

Q: Which workloads does the article say are driving demand for high core-count server CPUs like Venice?

The article says agentic AI and reinforcement learning workloads are driving demand for high core-count, high-throughput server CPUs like Venice.

The banners confirm eight compute dies surrounding two I/O dies, with each CCD packing 32 Zen 6c cores for 256 cores and 512 threads total.

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Hassam Nasir

Tech Reporter

Published Jul 22, 2026 10:10 PM CDT

1 minute & 15 seconds read time

TL;DR: Banners at Moscone Center reveal EPYC Venice's die: eight CCDs (each with two 16-core CCXs = 32 cores) around two I/O dies, totaling 256 cores and 512 threads. Venice uses Zen 6c layout, is first HPC product in TSMC 2nm volume production, and targets major perf/efficiency gains.

Voice: Hassam NasirSpeed

0:00 / 2:45

Ahead of CEO Lisa Su's Advancing AI 2026 keynote in San Francisco, AMD has begun showcasing its upcoming EPYC Venice processor. Banners installed around the Moscone Center West, photographed by ComputerBase, include a detailed rendering of the flagship 256-core Venice chip's internal layout, and it is a genuinely impressive piece of silicon.

The die shot confirms the structure AMD teased at CES earlier this year. Eight compute dies surround two large I/O dies at the center. Each compute die is a CCD containing two 16-core Core Complexes, giving each CCD 32 cores. Eight CCDs across 16 CCXs add up to 256 cores and 512 threads in the flagship configuration. The rendering shows cores arranged in a 2x4x4 layout within each CCD, consistent with the dense Zen 6c configuration used in the highest core count Venice processors rather than the larger standard Zen 6 cores.

AMD's 256-core EPYC Venice die shot has been spotted on Moscone Center banners ahead of Lisa Su's keynote 3

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Venice is the first high-performance computing product to enter volume production on TSMC's 2nm process, which transitions from FinFET to Nanosheet transistors and delivers 10 to 15% higher performance at the same power, 25 to 30% lower power consumption at the same performance, and up to 15% higher transistor density. AMD has promised more than 70% performance and efficiency improvement over its current generation EPYC Turin chips, alongside a more than 30% increase in thread density.

AMD's 256-core EPYC Venice die shot has been spotted on Moscone Center banners ahead of Lisa Su's keynote 2

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Question #1

What is the core and thread count configuration confirmed by the Venice die shot banners?

Question #2

What manufacturing process is Venice produced on and what transistor technology does it use?

Question #3

What performance and power improvements does AMD claim for Venice compared to EPYC Turin?

Question #4

Which workloads does the article say are driving demand for high core-count server CPUs like Venice?

Have a question not listed here? Ask below and TweakBot will answer it.

Agentic AI and reinforcement learning workloads are driving demand for high core count, high throughput server CPUs in a way that is pulling investment toward that space alongside GPUs. NVIDIA's Vera CPU is AMD's primary competitor here, and AMD has shown early benchmarks placing Venice well ahead. More details are expected during Lisa Su's keynote, where AMD is also expected to address its Helios rack-scale AI platform.