Ahead of CEO Lisa Su's Advancing AI 2026 keynote in San Francisco, AMD has begun showcasing its upcoming EPYC Venice processor. Banners installed around the Moscone Center West, photographed by ComputerBase, include a detailed rendering of the flagship 256-core Venice chip's internal layout, and it is a genuinely impressive piece of silicon.
The die shot confirms the structure AMD teased at CES earlier this year. Eight compute dies surround two large I/O dies at the center. Each compute die is a CCD containing two 16-core Core Complexes, giving each CCD 32 cores. Eight CCDs across 16 CCXs add up to 256 cores and 512 threads in the flagship configuration. The rendering shows cores arranged in a 2x4x4 layout within each CCD, consistent with the dense Zen 6c configuration used in the highest core count Venice processors rather than the larger standard Zen 6 cores.
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Venice is the first high-performance computing product to enter volume production on TSMC's 2nm process, which transitions from FinFET to Nanosheet transistors and delivers 10 to 15% higher performance at the same power, 25 to 30% lower power consumption at the same performance, and up to 15% higher transistor density. AMD has promised more than 70% performance and efficiency improvement over its current generation EPYC Turin chips, alongside a more than 30% increase in thread density.
- Read more: Leaked AMD Zen 6 EPYC Venice samples spotted with 64-192 cores across 1P & 2P setups on Congo, Kenya, and Nigeria Platforms
- Read more: AMD confirms next-gen EPYC 'Venice' Zen 6 CPU has 256 cores, will debut in 2026
- Read more: AMD shows off next-gen Zen 6-based EPYC 'Venice CPU, Instinct MI455X GPU for Helios AI racks
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Agentic AI and reinforcement learning workloads are driving demand for high core count, high throughput server CPUs in a way that is pulling investment toward that space alongside GPUs. NVIDIA's Vera CPU is AMD's primary competitor here, and AMD has shown early benchmarks placing Venice well ahead. More details are expected during Lisa Su's keynote, where AMD is also expected to address its Helios rack-scale AI platform.
