NVIDIA has announced NVHBM, a custom high-bandwidth memory architecture designed to push past the limits of standard HBM. Compared with HBM4E, NVIDIA says NVHBM can deliver up to 30% more memory bandwidth while cutting HBM power consumption by 15%. The biggest change comes from rethinking where the memory controller physically sits.
In conventional designs, the memory controller lives on the compute die itself. NVHBM instead moves the controller directly into the 3D HBM stack's base die. This frees up to 25% more space on the XPU for additional compute. NVIDIA says the approach also shrinks the physical memory interface, cutting the PHY and support area by up to 67% compared to the JEDEC HBM4E standard. That, in turn, can free up to 80% more usable silicon across the overall layout.
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These power savings could also make a difference at the data centre level. NVIDIA says that in a 1-gigawatt data centre running 2,000W XPUs, NVHBM's lower power consumption could create enough thermal and power headroom for up to 15,000 additional XPUs. NVIDIA also claims that the architectural changes can deliver roughly 30% more overall end-to-end performance per XPU.
NVHBM builds on NVIDIA's NVLink Fusion program, which lets partners combine their own silicon with NVIDIA processors within the same rack. Companies including Amazon, Marvell, MediaTek, Fujitsu, Arm, Cadence, and Samsung have already signed on to support NVLink Fusion.
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No products using NVHBM have been announced yet, and HBM4E itself has not shipped in any commercial product so far. NVIDIA's current Vera Rubin chips use HBM4. NVHBM is widely expected to debut with NVIDIA's next-generation Feynman GPUs, which are slated for 2028.
