Intel and AMD join hands to standardize APX extensions for x86 CPUs to improve efficiency and end ISA fragmentation

Intel and AMD have agreed to standardize the Advanced Performance Extensions (APX) for x86 CPUs, a move that could improve efficiency and reduce long-standing instruction-set fragmentation.

Intel originally announced APX in July 2023. Historically, the x86-64 standard has mandated 16 General Purpose Registers (GPRs). In a CPU, registers are small, fast storage locations within the processor that hold data temporarily during processing. Data is ultimately brought from memory and caches into these registers for execution.

By doubling the General-Purpose Registers (GPRs) from 16 to 32, the CPU keeps more data in flight. Intel claims this leads to 10% fewer loads and 20% fewer stores. APX also introduces three-operand instructions, allowing the CPU to perform calculations without overwriting the original data. Intel says this doubling improves performance without significantly increasing the die size or power consumption.

This announcement comes as Intel and AMD are co-authoring new ACE instructions. While ACE introduces new 2D Tile Registers for AI and Machine Learning, APX upgrades the general instruction set and streamlines everyday workloads.

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This collaboration, pioneered by the x86 Ecosystem Advisory Group (EAG), makes it easier for compiler developers to write the same enhancements for both CPU brands. Historically, Intel and AMD introduced competing or proprietary extensions, forcing developers to write separate code paths. By standardizing APX, a compiled binary gains the same benefits whether you run it on Ryzen or Core Ultra.

ARM's instruction set has traditionally been more consistent than x86, largely due to centralized control. EAG aims to eliminate this issue by standardizing features like APX across both vendors. As a result, developers are more likely to adopt APX, since they now see it apply uniformly across the entire x86 ecosystem rather than being limited to a subset of CPUs.

APX also improves branch misprediction handling by expanding the conditional instruction set, a feature Intel first introduced with the Intel Pentium Pro in 1995. This reduces the number of branches that may incur mispredictions. In addition, APX remains backward-compatible with existing x86 code, though older CPUs cannot run APX-only code.

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Changes to a program's source code are not expected. However, your existing binaries will need to be recompiled with a newer compiler to see the performance improvements APX offers. JIT (Just-In-Time) compiled applications will, however, see enhancements as soon as the runtime engine is updated and will likely not require developer intervention.

APX is expected to debut alongside Intel's high-end server chips, such as Diamond Rapids (Xeon 7), and its next-generation consumer products, such as Nova Lake (Core Ultra Series 4). For AMD, while APX adoption is planned, the specific timeline has not been finalized, so it is currently unclear if Zen 6 will include APX support.