Intel's Nova Lake will unify L2 cache and feature new 'D' and 'DX' lines for enthusiasts, claims leaker

Hardware enthusiast Jaykihn on X (formerly Twitter) has shared several details about Intel's upcoming Nova Lake CPUs. The leaker highlights major changes to the cache hierarchy, including a shared L2 cache, as well as the debut of the 'D' and 'DX' lineups for enthusiasts.

Nova Lake will succeed Intel's current Arrow Lake family and is set to arrive next year. The flagship features a dual-compute tile layout, reaching a massive 52 cores (16P+32E+4LPE). Alongside these high-core-count CPUs, Intel is expected to introduce specialized 'bLLC' models with up to 288MB of L3 cache. This move aims to rival AMD's X3D offerings.

For the first time in 17 years, Intel is reportedly moving away from its private L2 cache design, which has defined its CPUs since Nehalem. Clustering two P-cores with a shared 4MB L2 cache can cut ring bus stops and improve core-to-core communication within a cluster. There are downsides to this approach, but the goal is to raise core counts without letting bus latency spiral out of control. Notably, this shared cache is lower than the private 3MB L2 cache per P-core in Arrow Lake.

For standard non-bLLC variants, Intel keeps L3 cache figures consistent with the previous generation. A typical 8+16 die still contains 36MB of L3 cache, which breaks down to 6MB per two-core P-cluster and 3MB for each four-core E-cluster. The bLLC variants, however, see this figure bump up to 12MB. For the flagship 52-core CPU, the math gives us: the 8 P-core clusters contribute 192 MB, while the 8 E-core clusters add another 96 MB, bringing the total L3 cache to an impressive 288 MB.

Complementing the leaked specifications we saw several days ago, Intel reportedly plans to diversify its product segmentation with Nova Lake. Single-tile unlocked (K-series) variants with bLLC, such as Core Ultra 7 (8+12) and Core Ultra 9 (8+16), will be part of the new 'D' series. Dual-tile models with bLLC will be branded 'DX', which brings us back to Intel's consumer HEDT (Core-X) products. We aren't expecting a return to quad-channel memory or a major boost in PCIe lanes, but the 'DX' badge is likely for top-tier CPUs.

The leaker has revealed more information about the non-K bLLC model we covered earlier. This 65W Core Ultra 9 variant features 22 cores (6P+12E+4LPE) and 108MB of L3 cache. It offers a high-cache configuration without D/DX branding. So far, leaks show that bLLC variants exist only in the Core Ultra 7 and 9 lines. Whether this large cache will be available in Core Ultra 5 is unknown. In any case, we can expect more details from Intel at Computex in June.