AMD Ryzen Zen 6 CPUs to receive performance boost thanks to new design

AMD's Zen 6 architecture is expected to come with major power efficiency and latency improvements as Team Red seems to have implemented a new chiplet architecture that has already been showcased in the company's Strix Halo APUs.

The discovery was made by YouTuber High Yield, who pointed out in a recent video the architectural difference between AMD's Strix Point APUs and Zen 2,3,4, and 5 CPUs. Here's what was found. AMD currently uses what is called "SERDES PHYs" on the CCD (Core Complex Die) edges, the part of the CPU that contains the CPU cores. On the edge of these CCDs are high-speed serial lanes, which are used to communicate across the substrate, or the material that is beneath the dies.

SERDES PHYs is a serializer/deserializer, and AMD has been using this technique to communicate between chips since Zen 2. However, it appears that it will soon be changed. But first, here's how SERDES PHYs work in a nutshell. Data from the CPU cores is serialized into high-speed bitstreams, sent across the substrate, and then deserialized again on the other side. While this technique has worked well since Zen 2, it has two major downsides: it consumes extra power because the hardware has to encode/decode, clock recovery, and latency, as the data needs to be converted back and forth.

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Why not stick to this design if it's working so well? Well, AMD intends to add new components to its chiplet designs, such as GPUs and dedicated NPUs, which means the bottleneck for performance will be the communication between each of these chips. Here's where the performance jump comes in. High Yield points out that AMD has already showcased its next-generation chip architecture with its Strix Halo APUs, as it uses TSMC's InFO-oS packaging and redistribution layers (RDLs).

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Instead of converting parallel data into serial streams, AMD now runs many short, parallel connections directly between dies, removing the need for serialization and deserialization, which, in turn, reduces power draw and latency, while also allowing bandwidth to scale more easily by simply adding more connections between the chips. High Yield identified this change in AMD's Strix Halo architecture by noticing pads typical of fan-out wiring and also the lack of large SERDES blocks that were used in previous Zen architectures. This is why High Yield believes AMD will be adopting this interconnect architecture change in Zen 6.

Here's an analogy to break it down easily.

Think of AMD's old SERDES interconnect like a city that only has a handful of ultra-fast bullet train tracks between districts. Each train track (a SERDES lane) is narrow, but the trains run at extreme speed and carry a steady flow of passengers. To make this work, every time people want to board, they first have to convert into a train-friendly format-lining up, being scanned, and packed into carriages (serialization). On the other end, they get unpacked again (deserialization) before entering the next district. It works, but the boarding and unpacking process takes time and energy, and there are only so many train lines you can realistically build.

Now compare that to AMD's new fan-out interconnect with RDL. Instead of relying on a few bullet train tracks, the city builds a massive freeway system with dozens or even hundreds of regular lanes. Cars (data) just drive directly across without needing to be packed and unpacked. The speed of each car isn't as extreme as the bullet train, but because there are so many lanes running in parallel, the total traffic flow is much higher. More importantly, there's no costly conversion process-cars stay cars the whole time-which saves fuel (power) and gets people to their destination faster (lower latency).