AMD's next-gen RDNA 5 flagship gaming GPU pictured, 96 Compute Units, 512-bit memory bus

If you're like us and obsessed with PC hardware, gaming, and what's on the horizon, you probably know the name Kepler_L2. As one of the most trusted and respected leakers of GPU information, if they're posting anything related to specs or hardware, it's worth taking note of. The latest Kepler_L2 drop over on the Anandtech Forums (via Wccftech) offers images of GPU die configurations or block diagrams for AMD's upcoming RDNA 5 or UDNA generation of Radeon graphics.

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According to the image, the top RDNA 5 GPU will be a beast, featuring eight shader arrays and 16 shader engines, which deliver a total of 96 Compute Units. This would be AMD's flagship, a GeForce RTX 5090-like alternative, something it has chosen not to offer with its current RDNA 4-powered Radeon RX 9000 Series. There, the flagship Radeon RX 9070 XT features only 64 Compute Units.

The image also offers some insight into the memory configuration for AMD's next-gen flagship RDNA 5 or UDNA GPU, with 16 Unified Memory Controllers delivering a maximum bus or interface size of 512-bit. Now, will all of this hardware make its way into a commercial flagship Radeon RX 10090 XT desktop graphics card built for PC gaming? Or will it be limited to the workstation and AI space?

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Time will tell, but it does suggest that AMD is committed to offering a flagship GPU next time around, after choosing to skip that SKU with RDNA 4. Moving down the line, the following diagram showcases a GPU die with 40 CUs (Compute Units), along with the memory configuration pointing to a 192-bit interface. This represents a significant downgrade from the flagship configuration. Still, with RDNA 5 rumored to be built using a more advanced and efficient node, as well as adopting faster and more efficient GDDR7 memory, this image could ultimately be our first look at the successor to the Radeon RX 9070 XT.

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Moving down even further, we see images of RDNA 5's mainstream and entry-level dies with 24 and 12 CUs, respectively. Kepler_L2 also notes that RDNA 5 could feature bigger cache sizes per CU, which comes from the unified data center and consumer architectural design of UDNA. As part of its report on this new leak, Wccftech adds that a single RDNA 5 Compute Unit comprises a single RDNA 4 WGP (Work Group Processor). This would effectively double the CU counts that we're seeing here, similar to how NVIDIA's 'CUDA Core' counts doubled with the architectural changes introduced with its GeForce RTX 30 Series and Ampere architecture.