NVIDIA is reportedly considering the move to CoWoP (Chip-on-Wafer-on-Platform) PCB packaging for its next-gen Rubin R150 AI GPUs.

In a new report from Digitimes, their sources have said NVIDIA is looking into CoWoP PCB packaging for its next-gen AI GPUs, with CoWoP (Chip-on-Wafer-on-Platform) PCB removing the package substrate and connects the interposer directly onto the motherboard.
There are some major benefits to using CoWoP with Signal and Power integrity improvements, reduction in substrate losses, and bringing the voltage regulation closer to the main GPU die. These interfaces also increase the NVLink IC capabilities, while CoWoP packaging also doesn't require a package lid, which means the thermal solution is capable of making direct contact with the silicon. This means reduced costs as there's no need for a package lid, as it's eliminated with CoWoP.
NVIDIA looks to have been working on early tests of CoWoP this month, with its early test unit based on the GB100 GPU with a dummy GPU/HBM solution. We have a form factor of 110 x 110mm, with the goal being to evaluate the process flow selection.
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NVIDIA will reportedly begin testing on a functional GB100 CoWoP next month, with a functional GPU and HBM, with the unit keeping the same form factor and designed to evaluate the manufacturability, structural, electrical functionality, thermal design, and NVLink interface throughput. It will use an e6540 board and two GB102 GPUs, but no external customers will evaluate this, as NVIDIA is doing it in-house.
Moving into 2026, NVIDIA will debut its next-gen Rubin AI GPUs with the same CoWoP packaging, with reports that GR100 CoWoP will feature an SXM8 form factor, with the goals including Opportunistic POR and pipe clean for GR150. This means GR100 is the test bed that sets up for the full production-ready GR150 AI GPU.
NVIDIA's next-gen Rubin GR150 CoWoP solution will be ready for production in late 2026, with availability of Rubin GR150 expected in 2027.
NVIDIA moving into the use of CoWoP doesn't mean CoWoS (Chip-on-Wafer-on-Substrate) is going away, as they'll use both of the packaging technologies moving forward. It also doesn't mean CoWoP is absolutely superior, as the move to a totally new packaging technology means that the up front costs and preparing and setting up the supply chain is a huge job in itself, so CoWoP will add even more complexity and design changes to existing motherboards, with a rise in costs and production bottlenecks expected.
Some of the key benefits of CoWoP include:
- Better SI with no substrate losses and an increase in NVLINK reach
- Better PI due to better PDN (VR closer to GPU, lower parasitics)
- Better Thermals with lidless and direct die contact
- Reduced PCB Coeff of Thermal Expansion to address warpage
- Improved Electromigration
- Improved AISC cost (No Package, No Lid)
- Better serves the long-term vision of the Dielet model



