AMD is aiming for an insane 7.0GHz or more clock speed with its next-gen Zen 6-based Ryzen CPUs

AMD is reportedly targeting 7.0GHz or higher boost CPU clock speeds for its next-gen Zen 6-based Ryzen CPUs on the desktop, according to new leaks.

In his latest video, Tom from Moore's Law is Dead updates us on his latest insider information suggesting that AMD is "definitely achieving" at least 6.4GHz on Zen 6, while their goal is 7.0GHz, while that 7.0GHz CPU clock is "in the middle" of what AMD is trying to achieve with Zen 6.

AMD's next-gen Zen 6 "Olympic Ridge" desktop AM5 processors clocking in at over 7.0GHz would be a huge deal for the entire market: AMD the company itself, PC gamers, performance enthusiasts, and as another nail into Intel's CPU coffin. Olympic Ridge will arrive on AM5, which is another win for AMD as it won't be forcing consumers into a new chipset and motherboard, unlike Intel's next-gen processors.

AMD will be tapping TSMC and its bleeding-edge N2X process node, which will be most of the magic making these insane 7.0GHz CPU clocks possible. This is one of the first times AMD has made multiple process node jumps, with 3 node jumps to get to Zen 6. Zen+ to Zen 2 went from 12nm to 7nm, while Zen 4 was using TSMC N5P (that was 3 node jumps) that saw 4.35GHz to 5.7GHz, and now Zen 6 will eat up 3 node jumps to N2X.

TSMC itself considers N2X to be a better node jump for some customers over its N2P process node, and AMD is taking full advantage of that it seems with its next-gen Zen 6 processors and a possible 7.0GHz and above clock speed.

AMD's next-gen Zen 6 processors leaked so far:

Olympic Ridge & Gator Range: AM5 + FL1 sockets, TSMC N2X CCD chiplets + N3P IOD chiplet (or N6)

• N3P IOD = 2 x 12-core Zen 6 + 2-core Zen 5 LP = 26 cores total (24+0+2) targeting over 6.0GHz clock speeds (6nm IOD likely has no LP cores)
• There are references to both a TSMC N3P IOD without a decent iGPU, and also a TSMC N6 IOD with weaker (or no) graphics and less features. It's plausible that AMD will use N6 IODs for budget AM5 SKUs.
• 128-bit DDR5 memory controller

Medusa Point Big (MD51): FP10 socket, TSMC N2P CCD chiplet + N3P IOD chiplet (and/or N3P monolithic)

• Chiplet variant = 1 x 12-core Zen 6 chiplet + 2-core Zen 5 LP = 14 cores total (12+0+2) (may get Zen 5 LP instead of Zen 6 LP for time to market)
• Monolithic variant = 4-core + 8-core Zen 6c + 2-core Zen 5 LP = 14 cores total (4+8+2) (may get Zen 5 LP instead of Zen 6 LP for time to market)
• 8-16 CU RDNA 4 or 3.5 (+) iGPU (both architectures are referenced as possibilities, and there are different CU counts referenced between documents of different variants)
• 128-bit LPDDR5X memory controller
• There are references to both an "N2 powderdorn CCD" for "AI 9 products" and a "monolithic N3P die" for "AI 7 / AI 5" class products (it seems "MD51" includes both high-end and mid-range variants)

Medusa Point Little (MD52): FP10 socket, TSMC N3P monolithic

• 2 or 4-core Zen 6 + 4-core Zen 6c = 8-10 cores total (2 or 4+4+2) (AMD has not yet decided if they want to go with 2 or 4 "full" Zen 6 cores)
• 4 CU RDNA 4 or 3.5 (+) iGPU (both architectures are referenced as possibilities, and there are different CU counts referenced between documents of different variants)
• 128-bit LPDDR5X memory controller
• "MD52" is specifically listed as targeting "AI 5" and "AI 3" class products

Bumblebee (MD53): FP10 and/or FP8 socket: TSMC N3C monolithic

• 2-core Zen 6 + 2-core Zen 6c + 2-core Zen 6 LP = 6 total cores (2+2+2)
• 2-4 CU RDNA 4 or 3.5 (+) iGPU (both architectures are referenced as possibilities)
• 128-bit LPDDR5X memory controller
• "MD53" is specifically listed as targeting the "budget laptop" market

Medusa Halo (MD5H): FP12 + FP11 sockets, TSMC N2P core chiplets + N3P IOD chiplet

• 2 x 12-core Zen 6 + 2-core Zen 6 LP = 26 cores total (24+0+2)
• 48 CU RDNA 5 or 4 or 3.5 (+) iGPU (yes, there are references to possibly redefining the iGPU with RDNA 4 or RDNA 5 IP)
• RDNA 5 is targeting a very late 2025 or 2026 tapeout (it's not certain yet), and thus aligns with MD5 Halo maybe getting RDNA 5)
• 384-bit LPDDR6, 256-bit LPDDR5X memory controller (LPDDR6 has 50% more bits per channel)
• There is reference to (Little Halo) with a 192-bit LPDDR6 / 128-bit LPDDR5 memory controller and 24 CUs