AMD's next-gen Zen 5-based 'Strix Halo' FP11 package is as big as Intel LGA1700 size

AMD's next-generation Zen 5-based "Strix Halo" APU has had its package size leaked out, with the FP11 package matching the Intel LGA1700 desktop socket while being 60% bigger than AMD's own Phoenix APU.

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In some new leaks, we're learning that the FP11 package measures 37.5 x 45mm (1687mm2), which is identical to the LGA-1700 package used on Intel Alder Lake and Raptor Lake CPUs. Inside, AMD's next-gen Strix Halo APU will pack Zen 5 CPU cores and upgraded RDNA 3.5 GPU cores, with close to the same area used as the desktop AM5 and FP1 packages for Dragon Range, which are close to 1600mm2.

Over the years, AMD has developed multiple packages for its Ryzen offerings, with the current FP8 package being larger and used for the latest-gen Phoenix APUs measuring 25mm x 40mm.

The new FP11 package will house the enthusiast-grade Strix Halo APU, while the FP8 package is used for the Ryzen 8000 series "Hawk Point" APUs and the upcoming Ryzen AI 300 series "Strix Point" APUs that will launch later this month.

AMD mobile package sizes:

• AMD FP6: Renoir, Cezanna, Lucienne, Barcelo (25 x 35mm)
• AMD FP7(r2): Rembrandt/-R, Phoenix (25 x 35mm)
• AMD FP8: Phoenix, Hawk Point, Strix Point (25 x 40mm)
• AMD FL1: Dragon Range (40 x 40mm)
• AMD FP11: Strix Halo (37.5 x 45mm)

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The new Strix Halo APU will feature a chiplet-based design, with one or two Zen 5 CCDs and a huge SoC die that features an oversized integrated RDNA 3+ GPU, and 256-bit LPDDR5X memory controllers not found on the cIOD. AMD is aiming at CPU and GPU performance that competes with Apple's M3 Pro and M3 Max SoCs, at comparable PCB and power consumption.

AMD is using an integrated RDNA 3+ GPU in its next-gen Strix Halo APU, with a huge 40 Compute Units that works out to 2560 Stream Processors, 80 AI accelerators, 40 Ray accelerators, 160 TMUs, and an unknown amount of ROPs, with GPU clock speeds of up to 3.0GHz

AMD Ryzen AI HX Strix Halo APU expected features:

• Zen 5 Chiplet Design
• Up To 16 Cores
• 64 MB of Shared L3 cache
• 40 RDNA 3+ Compute Units
• 32 MB MALL Cache (for iGPU)
• 256-bit LPDDR5X-8000 Memory Controller
• XDNA 2 Engine Integrated
• Up To 60 AI TOPS
• 16 PCIe Gen4 Lanes
• 2H 2024 Launch (Expected)
• FP11 Platform (55W-130W)