ASML has announced more plans for a new lithography tool of the fut ure, something that will extend design limits for the very highest transistor-density chips.
ASML's former president, Martin van den Brink, surprised experts with the announcement of a next-gen "Hyper-NA" EUV lithography technology that is still "in the early stages of development," according to global R&D organization imec, which is working closely with ASML, reports EE Times.
ASML's former president, Martin van den Brink, said in a May presentation at imec's ITF World in Antwerp: "Moving forward long term, we need to improve our illumination system, and we have to go to Hyper-NA. In parallel, we have to drive the productivity on all of our systems to 400 to 500 wafers per hour".
High-NA takes numerical aperture (NA) to 0.55 NA from the 0.33 NA of earlier EUV tools, where around 3 years ago, ASML said High-NA would help chipmakers reach nodes well beyond 2nm for at least 10 years. Now, ASML is saying that they'll be offering Hyper-NA by around 2030, reaching 0.75 NA.
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According to Imec Advanced Patterning Program Director Kurt Ronse, who has developed lithography in cooperation with ASML for over 30 years, this was the first time that ASML added Hyper-NA EUV to its roadmap.
Imec Advanced Patterning Program Director Kurt Ronse, told EE Times: "There's a lot of research on going now. Can we go higher than 0.55 to 0.75, 0.85? Hyper-NA certainly brings some new challenges. If you go higher than 0.55, very quickly you see that polarization is killing your contrast, because one of the polarization orientations is basically canceling out the light. You would need polarizers in order to avoid that".
Two years ago, imec started working on Hyper-NA with computer simulations, with Ronse explaining: "Gradually you saw that more and more companies started to be interested in Hyper-NA and started their own studies. Zeiss were starting to make their lens designs, and gradually also ASML was becoming more open on Hyper-NA, but they never have put it on the roadmap before, as far as I know. It was always ending with 0.55 NA".
Ronse continued: "Already at 0.55 NA we will have thin down the resists. With Hyper-NA, it even gets worse. This will result in more challenges for etch selectivity".
Intel Foundry installed the industry's first High-NA EUV lithography machine -- made by ASML -- with Intel saying the new High-NA EUV lithography machine will allow the company to dramatically improve resolution and feature scaling for the next-generation of processors beyond the new Intel 18A node, which is "roughly equivalent" to TSMC's upcoming 2nm process.
TSMC is the world's largest contract chip manufacturer, making chips for the likes of AMD, Intel, Apple, Qualcomm, NVIDIA, MediaTek, and more. TSMC isn't using High-NA EUV lithography machines just yet, but the Taiwan semiconductor giant can use its expertise in double-patterning together with its current EUV tools, according to Ronse.
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TSMC has been meeting with ASML over the last few weeks about future EUV machines, so we'll see TSMC getting at least something -- we all know what it is -- from ASML in the future. Ronse added: "What is really critical in double patterning is the edge-placement error. Your two masks have to be perfectly aligned. Intel wants to avoid that. The big difference with Intel is that they have not mastered double patterning as well as TSMC. As a result, they prefer a higher resolution with High-NA EUV".
Samsung, Micron, and SK hynix are all considering High-NA EUV lithography machines, with Ronse adding that High-NA should last through process nodes going from 2nm to 14 angstroms, 10 angstroms, and even down to 7 angstroms. After that, Hyper-NA will start to take over.
Ronse says that Hyper-NA will reduce the "dangerous trend" of double patterning, adding: "If you do double patterning, you have to do everything twice. That easily becomes more expensive".