Intel Nova Lake CPU full leak: 52 cores, bLLC is Intel's answer to X3D cache, LGA 1954 socket

Intel's next-gen Nova Lake-S desktop CPU leaks: up to 52 cores with 16 Coyote Cove P-Cores, X3D competitor, new LGA 1954 socket and late 2026 release.

Intel Nova Lake CPU full leak: 52 cores, bLLC is Intel's answer to X3D cache, LGA 1954 socket
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TL;DR: Intel's upcoming Nova Lake-S desktop CPUs, launching in 2026, will feature up to 52 cores, advanced bLLC cache technology rivaling AMD's 3D V-Cache, and significant performance gains over Arrow Lake. Configurations range from entry-level 8-core to flagship 52-core models, promising up to 45% better gaming and multi-threaded performance.

Intel's next-generation Nova Lake-S desktop CPUs won't be here until 2026, but we've got some new leaks to share on Nova Lake-S with its up to 52-core configuration.

In a new video posted by leaker Moore's Law is Dead, we're hearing that the new Intel Nova Lake-S processors will feature 52 cores and 52 threads in total, something we've heard in previous leaks, with "bLLC" or "Big Last Level Cache" that is Intel's current answer to AMD's innovative (and kick ass) 3D V-Cache technology. The bLLC will be on-die L3 in the middle of the ringbus.

There are reportedly five Tiles on Nova Lake-S, with 2 x bLLC dies = 8+16 Compute Tiles, with MLID noting that we should expect games to only really utilize one bLLC Tile. We should expect the flagship Nova Lake-S processor to be made on TSMC's bleeding-edge N2P process node, with 52 cores + 144MB of bLLC per CCD for a huge 288MB of L3 cache in total.

The "premium gaming configuration" will feature 28C in total = 8+16+4 (8 Coyote Cove P-Cores, 16 Arctic Wolf E-Cores + 4 Low Power Arctic Wolf E-Cores) with a total of 144MB bLLC cache. The "mainstream configuration" will feature 8+16+4 cores again, but with just 36MB of L3 cache, while the "budget configuration" features 4+8+4 (16 cores total) with 18MB of L3 cache, while the "entry configuration" will be fabbed on Intel's in-house 18A process node with 4+0+4 (8 cores total) and just 12MB of L3 cache.

MLID says that he has seen some documents on performance regarding non-bLLC Nova Lake-S which is expected to deliver a 16% single-threaded and 12% multi-threaded uplift over Arrow Lake, while another doc says that the bLLC version will feature 20% single-threaded and 23% multi-threaded uplifts over Arrow Lake.

One of the simulations showed had the 52-core flagship Nova Lake-S processor with a 20% single-threaded uplift, and a huge 80% multi-threaded uplift, this is because it's 52C/52T versus Arrow Lake with just 24C/24T.

Nova Lake-S gaming performance was mentioned in a single document that MLID saw, mentioning bLLC Nova Lake-S outperforming Arrow Lake by 30-45%, and standard Nova Lake outperforming Arrow Lake by 10-15%.

MLID says that there's an "APO+" program that "attempts" to add another 15-25% gaming uplift on top of what's listed above, by forcing games to use specialized Intel optimizations, and also swap out outdated instructions for newer ones in the executable of the game itself. Intel is reportedly even considering providing a way to overwrite executables without the consent from developers that aren't directly patched.

The leaker says that this does indeed raise a ton of concerns of DRM compatibility concerns, but Intel "sounds determined to get close to Zen 6 in gaming in at least some popular titles", noting that this "still might not happen".

Top Nova Lake-S has 5 tiles:

  • 2 x bLLC dies = 8+16 Compute Tiles - Expect games to really utilize one lBBC Tile
  • 1 x Hub Die = North Bridge IP, Media Engine, Display Engine, NPU, Memory Controller, 4 x LPE Cores
  • 1 x PCD (Platform Controller Die) = South Bridge IP, TBT, Display Connections, PCIe, Security Engine, DMI to PCH
  • 1 x iGPU Die = 32 x Celestial Execution Units (Laptop UL/U/P/H/HX also have iGPU Tile options with 64 and/or 192 EUs)

The top half of the desktop lineup will be comprised of bLLC dies, with the bottom half having far less cache:

  • Flagship Configuration (TSMC N2P) = 52 Cores Total w/ 144MB of bLLC per CCD (288MB of L3 Total)
  • Premium Gaming Configuration (TSMC N2P) = 8+16+4 = 28 Cores Total w/ 144MB of bLLC
  • Mainstream Configuration (TSMC N2P) = 8+16+4 = 28 Cores Total w/ 36MB of L3
  • Budget Configuration (TSMC N2P) = 4+8+4 = 16 Cores Total w/ 18MB of L3
  • Entry Configuration (Intel 18A) = 4+0+4 = 8 Cores Total w/ 12MB of L3

Compared to ARL, the following performance details are noted in various docs:

  • One doc notes that non-bLLC NVL-S is expected to bring a 16% Single-Threading & 12% Multi-Threading uplift over ARL. (8+16 vs 8+16 Comparison)
  • Another doc states that the bLLC variant of NVL-S should bring a 20% Single-Threading & 23% Multi-Threading uplift over ARL. (8+16 vs 8+16 Comparison)
  • One simulation showed that the 52C flagship should bring a 20% Single-Threading & 80% Multi-Threading uplift over ARL. (52C vs 24C Comparison)
  • In gaming, one document mentioned that bLLC NVL should outperform ARL by 30-45%, and standard NVL should outperform ARL by 10-15%.
  • NVL-AX (Laptop AMD Halo Competitor) launches 2027 with 512EU or 256EU Celestial iGPU, 8+16 or 4+8 CPUs, and on-package LPDDR5X.
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Anthony joined TweakTown in 2010 and has since reviewed 100s of tech products. Anthony is a long time PC enthusiast with a passion of hate for games built around consoles. FPS gaming since the pre-Quake days, where you were insulted if you used a mouse to aim, he has been addicted to gaming and hardware ever since. Working in IT retail for 10 years gave him great experience with custom-built PCs. His addiction to GPU tech is unwavering and has recently taken a keen interest in artificial intelligence (AI) hardware.

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