SK hynix unveils DRAM memory chip roadmap for the next 30 years: 4F2VG tech, 3D DRAM, and more

SK hynix has teased its DRAM memory chip roadmap covering the next 30 years, which will include 4F2VG (vertical gate) technology that will improve DRAM chips, overcoming manufacturing challenges, with 3D DRAM as the "main driver" of its future growth.

SK hynix presented a new DRAM technology roadmap for the next 30 years and the direction for a sustainable innovation at the IEEE VLSI symposium 2025 held in Kyoto, Japan. At the event, Cha Seon Yong, the Chief Technology Officer (CTO) of SK hynix, delivered a prenary session on "Driving Innovation in DRAM Technology: Towards a Sustainable Future".

In this speech, CTO Cha said that it is getting more and more difficult to improve performance and capacity with scaling through current technology platforms. He said: "in order to overcome such limitations, SK hynix will apply the 4F² VG (Vertical Gate) platform and 3D DRAM technology to technologies of 10nm level or below with innovation in structure, materials, and components".

The 4F²* VG** platform is a next-generation memory technology that minimizes the cell area of DRAM and enables high-integration, high-speed and low-power through a vertical gate structure.

• 4F²: The area occupied by one cell, a unit to store data, is indicated as F2. F indicates the minimum feature size of a semiconductor. Therefore, 4F2 is an integration technology to put more cells in a chip which one cell occupies an area of 2F by 2F.
• VG (Vertical Gate): A structure that a gate, which acts as a switch of a transistor, is vertically placed and surrounded by channels. Currently, it is a flat structure where a gate is laid horizontally on top of channels.

Currently, 6F2 cells are common, but by applying 4F2 cell and wafer bonding technology that puts the circuit part below the cell area, cell efficiency and electrical characteristics can be improved.

CTO Cha introduced 3D DRAM as the "main pillar" for the future DRAM along with VG, adding that some of the industry warn of the cost increases according to the number of layers stacked, saying it can be solved by constant technological innovation.

CTO Cha said: "Until around 2010, DRAM technology was expected to face limitations at 20 nanometers, but with constant innovation, we have made it this far. SK hynix will continue to guide the future of long-term technological innovation to be a milestone for young engineers in the field of DRAM and maintain cooperation within the industry to bring future of DRAM into reality".