CPU, APU & Chipsets News - Page 143

I really have to stop reading about Intel's upcoming Xeon platforms, as I'm just going to disappoint myself that I'll never own one. The chipmaker is teasing its next-gen Xeon Skylake platform: Purley. The new architecture is going to be quite the leap over the current generation, with support for 6-channel DDR4, up from the quad-channel DDR4 support we have today.

Skylake Purley will be one of the biggest updates to the Xeon platform in quite a long time, with Skylake EX Purley supporting not just 6-channel DDR4, but up to eight processors that support 28 cores per chip, too. We also have the AVX 512 instruction set that will include the 100G OmniPath interconnect.

The OmniPath interconnect is something you've probably never heard of before, which is something that will be called Storm Lake. The PCH itself will be codenamed Lewisburg, with it sporting updated Ethernet controllers. The TDP that Skylake EX Purley processors will have will be between 45W and 165W, with CPUs slotting into something called Socket P. Another major update to the platform will see the number of PCIe slots increased to 48, with x4, x8 and x16 divisions allowed, which is a big upgrade to the platform.

Intel has said that the development of its 10nm technology is coming along well, with the chipmaker to begin talking about its plans for the future using 10nm later in the year.

President of Intel, Renee James, said during a recent Q&A session with stockholders at Intel's annual meeting: "The 10nm development is progressing very well. You will start to see start-up cost in the second half of the year on 10nm. We will talk about the timing of [10nm] later this year - the early part of next year about when that will happen".

We don't know much about Intel and its 10nm manufacturing process, but the company is wanting to increase transistor density, while reducing per transistor cost. This is something that other companies have failed to do with their shift into 14nm and 16nm FinFET processes, but Intel will hopefully see much more success with its 10nm technology.

Samsung is currently sitting at 14nm technology inside of its Galaxy S6 and Galaxy S6 edge smartphones, but we won't stay there for long if ARM has any say in the matter.

ARM is reporting set for the Ares core to hit just 10nm, something that will "reach smartphone and tablet makers by the end of next year". Ares will be here first with 10nm, but ARM is already teasing its successor: Prometheus. Prometheus will consume just 600-750mW of power, but Linley Gwenapp from analyst firm The Linley Group, believes that Ares will still have a place in the world.

Gwenapp said: "Ares core could reach smartphone and tablet makers by the end of next year. ARM is already well advanced on a next-generation high-end CPU that will follow the A72. In fact, this project is so far along that the A72 team could 'steal' some portions of the next-generation design. For example, a new floating-point unit reduces latency by 33%. The prefetcher, also from the next-gen design, improves the data-cache hit rate to boost performance. The next-gen branch predictor reduces mispredictions by 20%".

We aren't even half way through the year but we're hearing about what Intel will be releasing in the second half of 2016, according to a new leaked roadmap from the chipmaker.

Intel is expected to launch the Skylake architecture during Computex 2015 next month, something that will include the flagship Core i7-6700K processor. But what about 2016? Well, we are looking at Intel moving into their first 10nm processors with the new Cannonlake architecture, which should be an extremely low-power CPU, something that is going to really take flight in Ultrabooks. The mobile parts will come out in 10nm first, with desktop CPUs made on the 10nm arriving sometime in 2017.

Moving onto the HEDT side of things, Intel will release its next-gen High-End Desktop processor in Q3 2016 in the form of Skylake-E. Before that, we should expect Broadwell-E in Q1 2016, which will work on the current LGA 2011-3 socket. The new Skylake-E architecture will launch sometime in the second half of 2016.

Intel has just launched its new line of Haswell-EX Xeon CPUs, which include up to 36 threads (with the 18-core model), with up to 45MB of L3 cache, depending on the model.

The flagship Xeon E7-8890 V4 processor has 18 cores (36 threads), 45MB of L3 cache (LLC) and clock speeds that float between 2.5GHz and 3.3GHz in AVX workloads, and between 2.1GHz and 3.3GHz normally. This Haswell-EX powered Xeon CPU has a massive 165W TDP, packing some 5.6 billion transistors. All of this results in a wallet-busting price of $7175 or so.

The new Haswell-EX powered Xeon platform can handle up to 24 DIMMs per socket of either DDR3 or DDR4, with a full 8S server rack capable of consuming up to 12TB of DDR4 RAM. These new systems can handle up to 32 sockets, with 8-socket systems capable of taking 12TB of RAM, too.

As we begin to learn more about Intel's upcoming Skylake microarchitecture, the new 14nm-based chips are becoming more clear. We're now hearing details on the rumored Core i5-6600K and Core i7-6700K.

Starting with the Core i5-6600K which will have a total of four cores and no HT support, 6MB cache, a 3.5GHz clock speed (3.9GHz with Boost), 1600/2133MHz DDR3/DDR4 RAM support, Intel HD Graphics 5000 and a 95W TDP. The Core i7-6700K will feature four cores with four Hyper-Threaded cores, 8MB of cache, a 4GHz clock speed (4.2GHz with Boost), 1600/2133MHz DDR3/DDR4 support, Intel HD Graphics 5000 and the same 95W TDP. Both processors will slot right into the new LGA 1151 socket.

The rumored specifications are just that: rumors, especially considering the TDP sitting at 95W. We should expect some decent headroom for overclocking, with 4.5GHz being very easy for the Core i7-6700K to hit. WCCFTech is reporting that they expect something "major" with Skylake, and that it won't just be "another Haswell". We should learn more about Skylake as we get closer to Computex in the first week of June.

Intel has provided more details on its upcoming Xeon Phi line of processors, which will see up to 72 cores on a single processor, thanks to the Silvermont architecture. Not only that, but we can expect up to 384GB of DDR4, too.

Not only that, but the current prototype of the Xeon Phi coprocessor is capable of handling up to 32 cores, with each core capable of handling four threads for a total of 128 threads. Currently, we 8-core processors with 16 threads in total thanks to Hyper-Threading on the consumer side of the market. These new Xeon Phi processors would handle up to 36MB of shared L2 cache, and up to 16GB of the new stacked High Bandwidth Memory (HBM).

All in all, we can expect a six-channel DDR4 memory controller that can handle 2400MHz, and up to 384GB of DDR4 RAM. This is up from the quad-channel memory architecture we know and love with the X99 chipset from Intel, and the current flagship processor: the Core i7-5960X. It's interesting to note that we're seeing Intel move into HBM quickly.

Samsung is already pushing out 14nm technology, using its own Galaxy S6 and Galaxy S6 edge smartphones to demonstrate its impressive new fabrication technology. But most don't know that the South Korean electronics giant has partnered with GlobalFoundries, with the latter now spinning up its production of 14nm technology.

Mubadala Development Co. is an Abu Dhabi-based investment and development company that owns GlobalFoundries, with the company releasing a statement in regards to its 14nm production. Mubadala said: "GlobalFoundries announced a strategic collaboration with Samsung to deliver capacity at 14nm, one of the industry's most advanced nodes, as Fab 8 in Malta, New York began ramping production for customers".

Samsung developed both the 14LPE (low-power early) and 14LPP (low-power plus) technologies, licensing them to GlobalFoundries. Both of the manufacturing processes use FinFET transistors, but they still fall back on back-end-of-line (BEOL) interconnects which are fabricated on the 20nm node. Both fabrication technologies don't radically reduce costs of the chips compared to the previous-gen node, but they do provide a nice 20% boost in performance at the same power usage, or reduce power consumption by up to 35% without a performance hit.

It looks like AMD has some interesting things coming in 2016, with the current rumor is that its next-gen APU would arrive as a 16-core processor based on its Zen architecture, as well as a "Greenland" GPU with HBM memory.

The new APU will replace the Godaveri platform which we were introduced to with the Carrizo APU, with the Carizzo-based notebooks arriving in the next couple of months, but most likely at Computex 2015 in June. The new Zen APU would feature quad-channel DDR4 support, up to 16 processor cores based on the Zen architecture, and the HBM-powered Greenland GPU.

We should expect Greenland to be based on the Fiji architecture, which will be powering AMD's upcoming flagship video card: the Radeon R9 390X. We don't know if AMD will be using HBM1 or HBM2 on the Zen APU, but with the R9 390X using HBM1, we should expect AMD to quickly shift to HBM2 sometime in 2016.

We just got back from a briefing of the Knights Landing platform at Intel Jones Farm. This new platform compacts a large number of cores into a small package that consisted of 1U blades.

Here is the basic Knights Landing (KNL) information screen. Knights Landing will be based on 14nm process node and have a TDP of ~300watts. The number of cores shown on the slide shows over 60 cores, we assume there will be several different SKU's with different core counts and other spec's.

The KNL core itself is based on Silvermount, these cores have full Xeon capability and features which have been modified to meet the new design platform. The system itself will have both Windows and Lunix capability with very little code modification to applications if any. While running a Windows OS on this platform you can see all the logical processors in the task manager which shows the OS actually sees all the cores unlike Knights Corner which was a PCIe coprocessor.