The organization that handles the PCIe standards, PCI-SIG, have announced the release of the next-gen PCIe 6.0 standard which has some truly wicked next-level bandwidth.
PCIe 6.0 will offer up to 256GB/sec through a x16 PCIe 6.0 slot, and with advanced PAM4 technology (Pulse Amplitude Modulation with 4 levels) and many other new features and technologies, the new PCIe 6.0 standard is a huge step up from the already impressive PCIe 5.0 standard (which is huge over PCIe 4.0, and then PCIe 3.0, and so on).
The new super-fast PCIe 6.0 standard will usher in levels we've never seen before, with a x4 PCIe 6.0 M.2 NVMe SSD capable of 64GB/sec -- while if you had an AIC RAID card you could drive that up to an insane 256GB/sec -- untouchable levels with even PCIe 5.0, let alone PCIe 4.0.
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The new standard will be used for markets with heavy data transfers, including AI, data centers, machine learning, HPC (high-performance computing), IoT (Internet of Things), the military, and aerospace. PCIe 6.0 will include PAM4 signaling, low-latency Forward Error Correction (FEC), and Flit (Flow Control Unit)-based encoding.
Al Yanes, PCI-SIG Chairperson and President said: "PCI-SIG is pleased to announce the release of the PCIe 6.0 specification less than three years after the PCIe 5.0 specification. PCIe 6.0 technology is the cost-effective and scalable interconnect solution that will continue to impact data-intensive markets like data center, artificial intelligence/machine learning, HPC, automotive, IoT, and military/aerospace, while also protecting industry investments by maintaining backwards compatibility with all previous generations of PCIe technology".
Features of the PCIe 6.0 Specification
- 64 GT/s raw data rate and up to 256 GB/s via x16 configuration
- Pulse Amplitude Modulation with 4 levels (PAM4) signaling and leverages existing PAM4 already available in the industry
- Lightweight Forward Error Correct (FEC) and Cyclic Redundancy Check (CRC) mitigate the bit error rate increase associated with PAM4 signaling
- Flit (flow control unit) based encoding supports PAM4 modulation and enables more than double the bandwidth gain
- Updated Packet layout used in Flit Mode to provide additional functionality and simplify processing
- Maintains backward compatibility with all previous generations of PCIe technology
More key benefits of PCIe 6.0
- Double the Bandwidth: Increases the data rate to 64 GT/s, doubling the data rate of the PCIe 5.0 specification and providing a maximum bidirectional bandwidth of up to 256 GB/s for x16 lanes
- Low Latency: Utilizes fixed-size Flow Control Unit (Flit)-based encoding, which allows the use of a lightweight Forward Error Correction (FEC) with Pulse Amplitude Modulation with 4 levels (PAM4) signaling and a strong cyclic redundancy check (CRC) - with no impact to latency
- Backwards Compatibility: Maintains compatibility with all previous PCIe technology generations, protecting customer investments and supporting connectivity to millions of existing products
Greg Wong, Founder and Principal Analyst, Forward Insights said: "With the PCI Express SSD market forecasted to grow at a CAGR of 40% to over 800 exabytes by 2025, PCI-SIG continues to meet the future needs of storage applications. With the storage industry transitioning to PCIe 4.0 technology and on the cusp of introducing PCIe 5.0 technology, companies will begin adopting PCIe 6.0 technology in their roadmaps to future-proof their products and take advantage of the high bandwidth and low latency that PCI Express technology offers".
Ashish Nadkarni, Group Vice President, Infrastructure Systems, Platforms and Technologies Group, IDC said: "There is a growing demand for ever-increasing performance in many segments in the data center such as high-performance computing and AI. Within three to five years the application landscape will look very different and companies will likely begin updating their roadmaps accordingly. The advancement of an established standard like PCIe 6.0 architecture will serve the industry well in establishing composable infrastructure for performance intensive computing use cases".
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