HBM4 competition heats up as Samsung approves mass production of D1c process tech for HBM4

Samsung Electronics approves the mass production of its 6th-gen D1c DRAM, ready for HBM dies and will accelerate the development of HBM4 very soon.

HBM4 competition heats up as Samsung approves mass production of D1c process tech for HBM4
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TL;DR: Samsung Electronics has successfully developed its 10nm-class 6th-generation D1c DRAM process, enabling advanced HBM4 memory production. This breakthrough enhances chip stability, reduces leakage, and boosts competitiveness in the global DRAM market, positioning Samsung ahead in supplying next-gen AI GPUs and high-performance computing memory solutions.

Samsung Electronics has reportedly successfully developed a new DRAM chip using its 10nm-class 6th-generation (D1c) process technology, which will accelerate the development of HBM4 memory for the company.

The new D1c chip production will be used in the production process for HBM dies, which will help accelerate the development of its HBM4 memory, pumping some much-needed goodness into the competition of the global DRAM market.

Insider @Jukanrosleve picked up a new story that cites a source "well-versed" in the industry that said the Memory Business division of Samsung Electronics' Device Solutions (DS) group successfully developed the 6th-generation DRAM -- D1c -- and completed its internal Production Readiness Approval (PRA) this afternoon.

The new D1c process is the latest type of DRAM, classified as a sub-10nm-class ultra-fine process (approximately 12-13nm or less) and is subdivided by circuit line width into generations including 1x, 1y, 1z, 1a, 1b, and 1c, which you can read about in the links below.

Starting with Samsung's new D1c process, it can secure stability through a next-gen insulation structure and improved materials, minimizing the interference between cells. By changing transistor and contact materials, it's possible to reduce leakage current and secure process precision, allowing for the introduction of new materials.

D1c is also directly linked to competitiveness in HBM, with the High Bandwidth Memory standard increasing bandwidth and reducing latency by vertically stacking multiple DRAM dies using Through-Silicon Via (TSV) technology. The latest-gen DRAM process is essentially technology for stacking DRAM chips, with Samsung applying its new D1c to next-gen HBM -- HBM4 in this case -- Samsung is expected to be in a far better position than its competitors like SK hynix and Micron to (finally) pass NVIDIA's hard qualification tests.

Samsung kicked off the development of its D1c process back in 2021, conducting internal prototype tests for the last 2 years, announcing the world's first verification of D1c in February 2023. Now that Samsung has completed the successful development of D1c, the South Korean firm is expected to secure memory chip stability by expanding its application to HBM4 memory, AI server DRAM, and more in the coming years.

Samsung has been struggling to get a foothold in the HBM market, but this is a positive step moving forward for NVIDIA, AMD, and other big tech giants that are using HBM more and more. It's not just for more HBM, but more advanced HBM as we step through HBM3, HBM3E, and the upcoming new HBM4 and HBM4E standards later this year starting with NVIDIA's next-gen Rubin AI GPUs and AMD's upcoming Instinct MI400 AI chips.

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Anthony joined TweakTown in 2010 and has since reviewed 100s of tech products. Anthony is a long time PC enthusiast with a passion of hate for games built around consoles. FPS gaming since the pre-Quake days, where you were insulted if you used a mouse to aim, he has been addicted to gaming and hardware ever since. Working in IT retail for 10 years gave him great experience with custom-built PCs. His addiction to GPU tech is unwavering and has recently taken a keen interest in artificial intelligence (AI) hardware.

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