TSMC exploring 'radically new' semiconductor packaging technique called panel-level packaging

TSMC is exploring a 'radically new' semiconductor packaging technique: panel-level packaging, which has 3x more useable area than round silicon wafers.

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TSMC is exploring a 'radically new' method of semiconductor chip packaging, as the world of AI is simply not slowing down and needs further advancements at every level to keep up.

TSMC exploring 'radically new' semiconductor packaging technique called panel-level packaging 901

TSMC Is reportedly working with equipment and material suppliers on its new method, according to "multiple people with direct knowledge of the matter", reports Nikkei Asia. The new approach would use rectangular panel-like substrates, compared to the conventional round wafers of today. This new method is called panel-level packaging, which would allow more chips to be placed on each wafer.

The research into panel-level packaging is still early, and it would be many years before we see chips made on it, but it represents a "significant technical shift by TSMC" reports Nikkei Asia, which the company previously viewed using rectangular substrates as "too challenging".

For panel-level packaging to work, TSMC and its suppliers would need to devote a "significant amount of time and effort" to develop and upgrade multiple production tools and materials at its chip-making factories in Taiwan.

According to Nikkei Asia's sources, rectangular substrates in trials right now measure 510 x 515mm and have a usable area three times bigger than round wafers. The rectangular shape also means there would be less unused area at the edges, which is another win for panel-level packaging and TSMC.

TSMC was asked for a comment on the rumors, with the Taiwanese semiconductor giant replying that it "closely monitors progress and development in advanced packaging, including panel-level packaging".

One chip executive told Nikkei Asia: "The trend is certain. The size of the package will only grow bigger [as chipmakers] squeeze more computing power out of chips used for AI data center computing. But this is still at an early stage. For example, the coating of photoresists in cutting-edge chip packaging on a new shape of substrate is one of the bottlenecks. It takes the deep pockets of chipmakers like TSMC to push equipment makers to change equipment designs".

Mark Li, a semiconductor analyst at Bernstein Research, said TSMC might need to think about using rectangular substrates soon because AI chipsets are going to require more and more chips per package. Li said: "This shift would require a significant overhaul of facilities, including upgrades to robotic arms, and automated material handling systems to process the different shapes of substrates. This is likely a long-term plan spanning five to 10 years, not something achievable in the short term".

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NEWS SOURCE:asia.nikkei.com

Anthony joined the TweakTown team in 2010 and has since reviewed 100s of graphics cards. Anthony is a long time PC enthusiast with a passion of hate for games built around consoles. FPS gaming since the pre-Quake days, where you were insulted if you used a mouse to aim, he has been addicted to gaming and hardware ever since. Working in IT retail for 10 years gave him great experience with custom-built PCs. His addiction to GPU tech is unwavering and has recently taken a keen interest in artificial intelligence (AI) hardware.

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