Cadence teases PCIe 7.0 hitting 128GT/s with optical PCIe connections, successor to CopprLink

Cadence stole the show recently at the PCI-SIG DevCon 2024 event, and in honor of the 32nd anniversary of the PCI-SIG Developer's Conference, Cadence announced a complete PCIe 7.0 IP solution for HPC and AI markets of the future.

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Piper - Cadence PHY IP for PCIe 7.0 (source: Cadence)

The AI boom is creating a gigantic demand for faster-than-ever chips, which demand next levels of throughput, low latency, and power efficiency. This is fueling technology enhancements across the board, with Cadence being a close PCI-SIG member, the company says it has "valuable early insights into the evolving specs and the latest compliance standards".

HPC and AI systems of the future will require radically more bandwidth as that train never stops in the technology industry, especially for these important silicon-heavy environments. Direct GPU-to-GPU communication is absolutely critical for these systems, communicating heavy computational tasks across multiple GPUs or AI accelerators inside of a server or AI computing pod.

• Read more: PCI-SIG CopprLink cable specs for internal, external PCIe 5.0 and PCIe 6.0 connections
• Read more: PCI-SIG announces new naming scheme for PCIe cables: CopprLink
• Read more: PCIe 7.0 specs announced: SSDs will ramp up to 128GB/sec insanity
• Read more: PCIe 7 specifications highlight impressive 512 GB/s speeds and a launch window of 2027
• Read more: PCIe 7.0 specs released: 512GB/sec bandwidth total, next-gen PCIe 7.0 SSDs will pump 128GB/sec

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Industry's first IP subsystem for PCIe 7.0 (source: Cadence)

AI is very data intensive, and over time those applications -- and higher bandwidth, speeds, efficiency -- will evolve, which is where Cadence steps in with its PCIe 7.0 IP solution.

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Example of ASIC driving linear optics (source: Cadence)

In order to showcase its IP, the company demonstrated their subsystem test chip board for PCIe 7.0 that successfully transmitted and received 128GT/s signals through a non-retimed opto-electrical link configured in an external loopback mode with "multiple orders of margin to spare".

You can read the full (and very detailed) report from Cadence on its PCIe 7.0 IP solution here.

Cadence explained: "To showcase the robustness of Cadence IP, we have demonstrated that our subsystem testchip board for PCIe 7.0 can successfully transmit and receive 128GT/s signals through a non-retimed opto-electrical link configured in an external loopback mode with multiple orders of margin to spare".

"PCIe 7.0 specifications and beyond will enable the market to scale", adds Cadence, and that they look forward to helping customers build "best-in-class cutting-edge SoCs using Cadence IP solutions".