AMD Zen 6 leak: previous speculation is wrong, silicon bridges unleash performance says leaker

In the last week, we were hit with some incorrect leaks regarding AMD's next-gen Zen 6 die-to-die interconnect -- the "Sea of Wires" upgrade -- both those leaks were wrong says the most well-known Zen 6 leaker.

These leaks were wrong, with Moore's Law is Dead correcting the new speculations stating that AMD would be nerfing 3D V-Cache, or Zen 6 would be costing something like twice as much as Zen 5. MLID states Zen 6 will NOT have nerfed V-Cache, and it will NOT have some ridiculous cost over Zen 5.

MLID goes over his previous Zen 6 leaks from February 2025, where he said that both the CCD and IOD would be fabbed at TSMC on what he suspects to be its next-gen 2nm process node for the Zen 6 CCD cores. The leaker reiterated that Zen 6 would feature a bridge die beneath the CCD and IOD, which sees AMD fundamentally changing how the CCD and IOD communicates, massively reducing latency.

The leaker talked to one of his best industry sources at AMD who explained: "I saw odd speculation circulating online regarding Zen 6's interconnect, and as such I just wanted to reiterate that UMC makes the embedded silicon bridge, and also that SPIL is the OSAT for packaging. I must also note that much like V-Cache layers, the Silicon Bridge is nearly negligible in thickness and passive, and therefore I see no reason why it would mess with V-Cache in Zen 6, nor why it would be very expensive".

MLID's source continued: "This is a tech that we've (AMD) basically been using since MI200, and so I don't know why anyone would think we'd be scared to do it again in mainstream devices now that it's come down in cost. Which, on that last note -- Zen 6 Olympic Ridge, Medusa 1, and even Xbox Magnus all use silicon bridges. We could not afford to do that if it was expensive or prone to manufacturing bottlenecks".