Rambus Inc., one of the world's premier technology licensing companies specializing in high-speed memory architectures, today unveiled a set of innovations that can advance computing main memory beyond current DDR3 data rate limits to 3200Mbps. These innovations, available for licensing, build on Rambus' award-winning designs and include patented and patent pending technologies. Through this collection of innovations, designers can achieve higher memory data rates, higher effective throughput, better power efficiency and the increased capacity necessary for future computing applications.
"Product advancements in multi-core computing, virtualization and chip integration put ever-increasing demands on the memory sub-system, a key performance limiter in today's performance computing systems," said Craig Hampel, Rambus Fellow. "This collection of breakthrough innovations from Rambus allows for memory systems that are better suited for the bandwidth and workloads of these throughput-oriented multi-core processors, increasing the design and solution space for future main memory to enable a new generation of computing platforms."
The Rambus key innovations to advance the main memory roadmap include:
- FlexPhase Technology - introduced in the XDR memory architecture, can enable higher data rates compared to direct strobing technology used in DDR3;
- Near Ground Signaling - supports high performance at greatly reduced IO power, allowing operation at 0.5V while still maintaining robust signal integrity;
- FlexClocking Architecture - introduced in Rambus' Mobile Memory Initiative, reduces clocking power by eliminating the need for a DLL or PLL on the DRAM;
- Module Threading - increases memory efficiency and reduces DRAM core power, and when combined with Near Ground Signaling and FlexClocking technology, can cut total memory system power by over 40%;
- Dynamic Point-to-Point (DPP) - provides a path for capacity upgrades without compromising performance through robust point-to-point signaling.
Rambus licenses its broad portfolio of patented innovations for use in its leadership and industry-standard chip interface solutions, as well as industry defined interfaces.
Last updated: Apr 7, 2020 at 11:59 am CDT
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