Apple's next-gen M5 chip will use TSMC SoIC advanced packaging for future Macs, AI servers

Apple is gearing up to use TSMC's latest SoIC advanced packaging technologies for its next-generation M5 chips as part of a two-pronged strategy for the company to power its future Macs and AI servers.

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In a report from DigiTimes, we're learning that Apple would adopt TSMC's new SoIC (System on Integrated Chip) advanced packaging technology that allows for 3D stacking of chips, providing improved electrical performance and thermal management versus traditional 2D chip designs.

The Economic Daily reported that Apple has expanded its cooperation with TSMC on its next-generation hybrid SoIC packaging designs that combine thermoplastic carbon fiber composite molding technology, which is reportedly in a small trial production phase. Apple hopes to have TSMC mass producing its next-gen M5 processors in 2025 and 2026 for future-gen Mac system and AI servers.

• Read more: NVIDIA, AMD reserve all of TSMC's CoWoS, SoIC advanced packaging for 2024, 2025
• Read more: Apple executives 'secretly visit' TSMC to secure first batch of 2nm production capacity
• Read more: TSMC shows off 2nm chips to Apple, mass production expected in 2025 for the iPhone 17 Pro
• Read more: TSMC says its next-gen 2nm mass production begins in 2025
• Read more: TSMC to expand advanced packaging capacity at 3 plants: CoWoS, SoIC, SoW for AI GPU demand

Apple is reportedly powering its AI cloud servers with multiple connected M2 Ultra chips, which were designed to run on desktop Macs. But, if the next-gen M5 processor is used, the dual-use design could help Apple better future-proof its plans to vertically integrated its supply chain for AI functionality across Macs, cloud servers, and software.

TSMC's advanced packaging technologies include 2.5D CoWoS and 2.5D/3DInFO, with the most complex of them all being the 3D-stacked integrated chip system technology known as 3D-SoIC, which is a front-end 3D package. TSMC will reportedly rapidly develop its SoIC-X advanced packaging technology, where by 2027 the Taiwanese semiconductor giant will have wafers connected using 3μm bonding pitch through silicon via (TSV) which is 3x the density of the current 9μm pitch size.