TSMC's new 2nm node progressing smoothly: matching 5nm, surpassing 3nm, 7nm at similar stages

TSMC's next-gen 2nm process node (N2) is progressing smoothly, with defect density (D0) matching its 5nm process, and surpassing its 3nm and 7nm nodes at similar stages of development.

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We can expect mass production of TSMC's new 2nm process node in Q4 2025 according to the latest reports from Taiwanese media outlet Ctee, with AMD's new EPYC "Venice" CPU being the first to complete tape-out on 2nm, and Apple's next-gen iPhone 18 expected to use 2nm chips. Intel is also reportedly using TSMC's new 2nm process node for the compute tiles on its next-gen Nova Lake CPUs.

TSMC's list of 2nm clients includes Apple, NVIDIA, AMD, Qualcomm, Intel, MediaTek, and Broadcom. NVIDIA's next-gen Rubin AI GPU family will arrive on 3nm at first in 2026, with a refresh possibly hitting 2nm in the future. TSMC chairman C.C. Wei recently emphasized that demand for 2nm is "unprecedented" and far exceeds the demand of 3nm.

TSMC's new 2nm process node is the first time the company will be using all-around gate transistor (GAAFET) architecture, replacing the FinFET technology that has been used for many years now. GAAFET uses a 3D-stacked nanosheet structure that completely covers the transistor channel with gate material, improving transistor density and performance, as well as reducing leakage current and power consumption.

After the 2nm process is here, we'll see TSMC's next-gen A14 process node that will have 2nd generation nanosheet transistors, and more, with 10-15% more performance-per-watt, another 25-30% power reduction at the same clocks, and more. TSMC recently detailed its future-gen A14 process node at the recent North American Technology Symposium, with A14 expected in 2028.