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DDR4 Memory Overclocking Report and Beginner's Guide (Page 3)

By: Steven Bassiri from Jan 6, 2015 @ 7:10 CST

DDR Timing Investigation

First comes first: the easiest parameter to change for memory is the command rate. This is usually indicated in the UEFI as CR1 or CR2 (sometimes T1 or T2).

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I tested both the Crucial and the G.Skill kit at high and low speeds. It is obvious that CR makes a big difference, just as it did on DDR3. It was actually quite easy to change this - you might not even need to increase the voltage.

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Note that I didn't touch any of the other timings, and they are super loose at 32x in comparison to lower dividers. This graph illustrates the need to change other timings as well for maximum performance, but also shows us that just changing the CAS latency can have a positive effect.

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This is the typical DDR4 startup sequence for calibration. You will notice that the word "training" pops up a lot throughout the sequence. Signals don't always reach their destination at the same time, so small delays are introduced to ensure that all signals are synced the way they should be. Training allows for a testing and determination of the best possible range for the delay and signal. With DDR4 training, the DQ line can be customized to maximize margins, and the VRef is now internal and needs to be trained as well. It is also important to note here that RTLs and IOLs cannot be changed after boot up, and that will have an impact on the CAS latency if you change it in Windows.

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If you want the memory to train, then make sure to disable things like this option for fast booting, as it may skip parts of the DDR calibration procedure. You can also clear your CMOS, load your settings, and then save and exit, and that should ensure training (as opposed to changing something small and restarting).

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This is what happens if I boot up at auto timings (19-17-17-44), and then change them in Windows (marked as "Untrained"). The results are much better when I set the timings in the BIOS (marked as "Trained") from a clean CMOS reset.

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So, is it better to use the 1.00x divider, or the 1.25x? In general, when you use the 1.25x divider, you also use a lower memory multiplier to achieve the same speed like I did above. This means two things: first, your 3rd timings are tighter, and performance is improved; and second, your 3rd timings are tighter, and your maximum speed has decreased. There doesn't seem to be a huge difference between the two dividers; I would say they are pretty much equal. I would suggest that for very high-speed DIMMs, stability might be better with the 1.25x divider, as the tuning on higher multipliers might not be perfect when compared with lower multipliers.

Single vs. Double-sided

With DDR3, it is apparent that single-sided modules overclock higher, but don't perform as well at the same speeds as double-sided DIMMs. I decided to see if that was true for DDR4, so I took my two single-sided 16GB kits, and mixed them, filling up all eight DIMMs.

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The results show that double-sided DIMMs do provide some improvement over single-sided. However, having all eight DIMMs filled up also puts a strain on the IMC, and certain internal timings that could also slow down the single-sided tests are changed. If you are in the market for 32GB, I would go with a kit of four sticks, instead of one with eight.

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