Synopsys and Samsung achieve production tapeout of next-gen Exynos SoC on new 3nm process node

Synopsys and Samsung have announced its hit first production tapeout of its next-generation flagship mobile CPU on Samsung Foundry's GAA process.

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The companies announced that they have achieved successful production tapeout for its high-performance mobile SoC design, including flagship CPUs and GPUs, with 300MHz higher performance using Synopsys.ai full stack AI-driven EDA suite and a broad portfolio of Synopsys IP on Samsung Foundry's latest Gate-All-Around (GAA) process technologies.

Kijoon Hong, vice president of SLSI at Samsung Electronics, said: "Our longstanding collaboration has delivered leading-edge SoC designs. This is a remarkable milestone to successfully achieve the highest performance, power and area on the most advanced mobile CPU cores and SoC designs in collaboration with Synopsys. Not only have we demonstrated that AI-driven solutions can help us achieve PPA targets for even the most advanced GAA process technologies, but through our partnership we have established an ultra-high-productivity design system that is consistently delivering impressive results".

Shankar Krishnamoorthy, General Manager of the EDA Group at Synopsys, said: "The relentless demand for ever-better PPA and energy efficiency in high-performance mobile chips is driving the need for high-performance core-specific EDA optimization across the full stack. Our extensive set of PPA-boosting capabilities targeted for CPUs and GPUs across the Synopsys AI-driven EDA suite and IP portfolio enables our mutual customers to successfully design chips with the highest quality-of-results for the most advanced Samsung GAA processes".

To achieve the stringent performance and low-power requirements for Samsung's mobile SoC design, Samsung used Synopsys' award-winning Synopsys.ai EDA suite, utilizing Synopsys Fusion Compiler™ RTL-to-GDSII solution for superior PPA paired with Synopsys DSO.ai™ to further optimize design targets and maximize quality of results. High-performance core-specific techniques such as design partitioning optimization, multi-source clock tree synthesis (MSCTS), advanced wire optimization to minimize crosstalk and virtual-flat hierarchical solution in the Synopsys Fusion Compiler solution enabled Samsung to achieve 300MHz higher performance than alternative approaches and achieve 10% lower dynamic power, all while saving Samsung weeks of manual design effort.