During Intel's Architecture Day briefing they teased a new interconnect technology, which aims to replace EMIB as their go to for linking and even stacking devices on a package.
The new technology allows Intel to put an IO hub, power management, and say cache on a bottom layer, then put of 10nm x86 CPU with iGPU on top of that layer, and then put some DRAM on top of that, and take all those stacks and put them on a package.
Intel has made great improvement since EMIB. They reduced bump pitch to 36um from 45um, increased density from 560/mm2 to 828/mm, and cut power consumption in half. FOVEROS is awesome in that it allows for 3D face-to-face stacking for integration of many different types of devices on an active TSV interposer, which then sits on the package.
Why does FOVEROS exist? Intel told us a vendor wanted a chip for a mobile devices that integrated a 10Nnm CPU with a 10nm iGPU on top of a base die with cache and IO, and then toss in DRAM layers on top. Basically, a three layer stacked hybrid-x86 architecture on a package measuring 12x12mm. The result is a highly dense device smaller than a dime.
- >> NEXT STORY: Intel Xe: scalable graphics architecture aims for PETAFLOPS
- << PREVIOUS STORY: Intel Sunny Cove uArch: Deeper, Wider, Smarter. Bye Skylake!