The 3D V-NAND Capacity Breakthrough
Samsung V-NAND Moves into the Future
Planar NAND is reaching a diminishing point of returns, and the consensus is there are only a few die shrinks left before it is no longer financially viable. Current planar NAND designs feature a maximum density of 128Gbit per chip, but V-NAND is expected to enable up to 1Tb per chip by 2017.
Samsung V-NAND provides numerous paths forward that are free of the restrictions associated with smaller NAND lithographies. Coupling V-NAND with 3-bit per cell technology will provide an additional boost in density and capacity, and the enhanced endurance of V-NAND will help offset the inherent endurance reduction that results from storing more bits per cell. Current projections focus on increasing density by adding layers, but there is also the possibility of pairing higher vertical stacks with die shrinks in the future.
In May of 2014, Samsung began full-scale production of 32-layer V-NAND at their fabrication line in Xi'an, China. This 2.5 million square foot facility is roughly the size of 40 football fields. The facility was operational in a short time span of only 20 months, and will be completed within the year.
A key benefit of utilizing 3Xnm NAND is the reduced price of lithography tools compared to 20nm and smaller process nodes. The lack of patterning during production of CTF flash helps reduce manufacturing cost and complexity. The Xi'an facility will utilize much of the tooling used in the previous generation 24-layer NAND, and as Samsung continues to scale vertically, the reduced tooling and equipment costs will yield a significant cost benefit to consumers.
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- Page 1 [Introduction: The V-NAND Paradigm Shift]
- Page 2 [Scaling Challenges of Planar (2D) NAND]
- Page 3 [An Innovative Solution: 3D V-NAND]
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