SanDisk X210 Architecture
The eight-channel Marvell 9187 controller is the catalyst that powers the X210. Marvell does not provide firmware for their controllers, and SanDisk's proprietary firmware works in conjunction with their 19nm ABL NAND to provide enhanced functionality. SanDisk and Toshiba, through their Flash Forward initiative, have developed ABL (All Bit Line) NAND to provide twice the parallelism in comparison to standard HBL (Half Bit Line) NAND.
The addition of the nCache layer is a big advantage for the X210. The small layer of SLC, with its 100,000 P/E Cycles, acts as a cache for the MLC, with its mere 5,000 P/E Cycles. Small random writes are intelligently cached to the SLC buffer and combined into large blocks, and these blocks are then written sequentially to the MLC NAND. Sequential writes actually wear NAND less than random writes, helping to boost the longevity of the MLC by lowering the random write workload.
Caching also speeds up the initial burst of random write activity to the SSD. In operating system environments (bursty), one of the target markets for the X210, this can result in snappier response times. The X210 also features another layer of DRAM cache, typically used for caching tables.
The maximum power consumption of the X210 during read operations is 3.0 Watts, and 4.6 Watts for heavy write workloads. While the SSD idles, it will draw a mere 80 mW. Once the X210 enters into DEVSLP mode, it sips power at 5 mW, enhancing efficiency and boosting battery life in mobile applications.
The X210 features an MTBF of 2,000,000 hours, and an UBER rating of 10E16. The SSD is backed with a five-year warranty.
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- Page 1 [Introduction]
- Page 2 [SanDisk X210 Architecture]
- Page 3 [SanDisk 256GB X210 Internals]
- Page 4 [Test System and Methodology]
- Page 5 [4K Random Read/Write]
- Page 6 [8K Random Read/Write]
- Page 7 [128K Sequential Read/Write]
- Page 8 [Database/OLTP and Webserver]
- Page 9 [Final Thoughts]
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