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SATA 6G Implementation Preview - Ironing Out The Creases

Sean looks into the implementation of the new generation SATA 6G interface, the issues it brings with it and the ways around them.

| Editorials in Storage | Posted: Nov 3, 2009 6:20 am

SATA 6G is the next big drive transfer standard. As it stands right now Marvell is the only company with an available controller. Because of this we see them being hastily added to motherboards. In their first run the controllers failed to provide the anticipated performance and caused stability issues on the P55 boards they were placed on. These were quickly removed and the P55 was launched without SATA 6G.

 

However, the issue was and still is one of implementation. You see, the P55 Express chipset only has PCI-e Gen 1 lanes in it. All of the PCI-e Gen 2 lanes were moved to the Lynnfield CPU. This is normally okay as the only AIB (add in boards) that need this much bandwidth are graphics controllers. Not a problem, right? - Actually, it is a big problem.

 

In most cases a SATA II controller can use a single PCI-e lane for its transfer needs. As each PCI-e Gen 1 lane can handle up to 250MB/s (theoretical) and most SATA II drives (except for SSDs) are not capable of maxing even this out, there is no problem. Most people will never notice the missing 50MB/s at the top end as their drives are not capable of pushing more through the controller anyway.

 

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So what of SATA 6G? - It eats up a hefty 600MB/s (theoretical) running on a single PCI-e Gen 1 lane, which means you lose 350MB/s; something you are bound to notice. But there is something even larger at stake here. When we tested the external PCI-e x1 SATA 6G controller on the ASRock P55 Deluxe, we saw performance that was less than 100MB/s when this controller was plugged into the only PCI-e x1 slot. We asked ASRock about it and were told that we would need to use one of the Gen 2.0 slots on the board. Okay, this is all well and good as even a single PCI-e Gen 2 lane has 500MB/s available. We tried this and we saw our performance go back to where it should have been.

 

But there was an issue that we did not see back then, even though we should have. As the PCI-e Gen 2.0 lanes are all on the CPU, we were affecting GPU performance now. You see, any time you place something in the second PCI-e Gen 2.0 slot the motherboard is going to cut the available lanes to the primary slot down to eight. This means that despite only having a PCI-e x1 card in that slot, we are pulling seven extra lanes away from the primary slot. This is not a good way to fly and makes using the SATA 6G card for gaming enthusiasts a non-option.

 

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So what do you do to prevent this? - Well, you can do one of two things. You can try to bridge in four PCI-e x1 (Gen 1) lanes into the SATA 6G controller, or you can do what ASUS is doing. You take a leaf from NVIDIA's book and use a bridge.

 

This is probably the best short-term solution. However, things are a little different now. Instead of adding a bridge chip that allows for additional runs to the Northbridge and CPU, the new method allows the SATA 6G and USB 3.0 controller a single point of connection while the bridge uses four Gen 1 PCI-e lanes to talk back to the P55 or X58.

 

The bridge that ASUS is planning on using (and indeed the one that is on the P7P55D Premium) is a PEX PLX8613. This provides a single PCI-e x1 Gen 2 lane to the Marvell 9123 controller, providing 500MB/s maximum bandwidth. From there it connects back to the P55 using four Gen 1 lanes for a total of 1GB/s (4x250MB/s). The ASUS will use a bridge on future motherboards to connect the USB 3.0 (NEC D720200F1) controller with a single PCI-e Gen 2.0 lane to give it the bandwidth it needs. We are not sure if this will be the same PLX8613 or a different bridge chip as of this writing.

 

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To us this seems like the best method moving forward and the one that ASUS will be using in their E refresh for the P7P55D. Of course, once Intel moves the SATA 6G and USB 3.0 controllers into the chipset, all bets are off and the game will start again. Still, until then we at least know that we have a viable solution that does not force us to make choices in the way we use our systems.

 

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