Version and / or Patch Used: 188.8.131.52
Silicon Motion SM2256 with Toshiba A19 TLC
Samsung 840 EVO 250GB
The first thing everyone is going to call for is a show down between the new SMI SM2256 with Toshiba A19 TLC and Samsung's 840 EVO 250GB. This is a preview and not a pissing contest, but I did have some 840 EVO 250GB data with me.
The SMI drive is on the top and the EVO is on the bottom. The two test systems are not identical, so I'm going to limit comparison to this one graph. Both of these tests are ran in the same order, with sequential and random reads and writes taking place before HD Tach was ran and in the exact same order starting after a secure erase cycle.
The SMI drive had an average read speed of 475.7 MB/s and the 840 EVO 250GB had an average sequential read speed of 305 MB/s. Before the flash dropped down into what I call a consumer steady state, the SMI model floated between 305 and 225 MB/s. The 840 EVO was between 405 and 345 MB/s.
Version and / or Patch Used: 3.0 TP1
I'm a bit surprised by the numbers delivered in CDM. At first I thought I pulled up a result from Crucial's MX100 256GB, the results are very close to one another.
To see SMI's R&D board already running toe to toe with Micron's Marvell controlled, 16nm flash SSD this early on is somewhat shocking.
Anvil Storage Utilities
Version and / or Patch Used: 1.1.0
0-Fill Compressible Data
The SM2256 doesn't use compression technology to increase data writes, but that also means it doesn't slow down with incompressible data. The performance measured in Anvil isn't all that impressive compared to today's hyper-class SSDs like the 850 Pro and Extreme PRO, but it's in line with mainstream SSDs on the market right now.
We suspect the SM2256 will get a performance boost in the random data department before it goes live sometime in Q4. Our QD32 random 4K read result was just over 70K IOPS and our random 4K write result was 78K IOPS.
Read Disk Latency
The 64KB average read access time held true at .11ms in our aging AIDA64 test used in the preview articles.
Write Disk Latency
In the write latency test, we're looking for any tiered stepping. This is a really good test when trying to find a SLC-like cache layer. With TLC, manufacturers may even be able to run a MLC-like cache layer to increase system responsiveness.
We don't know for sure if the SM2256 R&D board uses either, but it did bring up an interesting topic for later discussion with manufacturers. Is it actually possible to run a larger MLC cache layer in the same space as a smaller SLC-like layer?
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- Page 1 [Introduction & Specifications, Pricing and Availability]
- Page 2 [Silicon Motion SM2256 Controller]
- Page 3 [Toshiba A19 3-bit per cell TLC Flash & Shots Fired]
- Page 4 [Silicon Motion SM2256 256GB R&D Board]
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