One of the most basic requirements for any storage device is the ability to identify and repair data errors. Denser and more cost-effective NAND technologies, such as TLC NAND and smaller NAND lithographies, come with increased bit error rates. Traditional SSD error correction implementations utilized BCH ECC to combat data errors, but higher bit error rates have led to LDPC (Low Density Parity Check) development. LDPC features two levels of error correction, hard-decision and soft-decision, which enhances correction capability, and reduces latency. Real-time LDPC requires more compute power than BCH ECC, and a tradeoff is that decoding circuits are larger and consume more power as a result.
LDPC has several advantages to previous error correction approaches, but Toshiba has taken a divergent path with their proprietary QSBC (Quadruple Swing-By Code) error correction technology. Flash controller manufacturers are developing custom LDPC algorithms, and each will feature different characteristics, so a direct comparison of the varying approaches is not entirely possible. Many of the details on custom LDPC codes, along with QSBC, are closely guarded intellectual property.
The graphic above indicates the error correction capability of three typical implementations. Typical Mini-Sum LDPC offers a 2x increase over BCH, but Toshiba's QSBC outpaces Mini-Sum LDPC by 8x. Toshiba has a long history with manufacturing NAND and overcoming errors, so it is not surprising that they already have an advanced proprietary solution integrated into their products.
Toshiba also utilizes End-to-End error detection and correction to protect every step along the data path, and NAND flash.
PLP and PFM
SSDs utilize cache layers to boost performance, but the cache is typically volatile DRAM that is susceptible to power loss. Power loss results in data loss, if there is not a mechanism to commit all data to the NAND when the SSD loses power. Drive management tables (LBA tables) and the firmware can also be compromised during power loss. Protecting data during power loss requires capacitors, and firmware optimizations.
The HK3R2 features both PFM (Power Fail Management) and PLP (Power Loss Protection). The Toshiba PLP implementation features a detection circuit that detects power loss and notifies the firmware, which then activates the Power Line Switch to shift power to the onboard capacitors. The SSD immediately initiates a rapid shutdown, and flushes cached data to the NAND.
PFM works in tandem with PLP to protect the internal management tables. Redundant copies of the management tables are stored on different physical NAND pages, and updates to the tables are alternated between the copies. The system simply restores the redundant copy during power-up if a table is corrupted. PFM also ensures that all data in the cache is flushed every two seconds during idle periods, and that new data is always written to a different NAND page. Toshiba validates every Toshiba SSD with PLP and PFM through 30,000 power cycles during their internal RDT process.
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