The benefits of deploying flash within the parallel memory subsystem, and keeping I/O in the CPU where processing and applications reside, are apparent in this graphic. Typically, data is DMA'd back and forth between the memory and storage subsystems, but with the MCS Carbon1 architecture, all I/O requests and completions are confined within the NUMA architecture, and can operate at the speed of the memory bus. Leveraging the memory subsystem of the processor gives MCS access to a scalable architecture that avoids the software/hardware I/O stack, and does not allow degradation or diminishing returns as it scales.
In contrast, the multi-purpose PCIe bus wasn't specifically designed for storage traffic. I/O incurs latency as it traverses the gap between the memory subsystem and the I/O Hub. The I/O Hub is restricted to one processor that handles all PCIe traffic, creating device contention with high performance add-in cards. MCS circumvents the HBA/RAID controller layer for routine data processing, and operations are simply a copy from one address to another within the memory subsystem.
The low latency MCS kernel driver routes requests through the CPU to the MCS Memory Space. The driver emulates SCSI in Windows and VMWare environments, and bypasses SCSI/SATA in Linux. The driver thread handles remapping, generates commands, posts them to the device, monitors the status, and copies data. MCS processes requests asynchronously, and the driver handles SMART logs, thermal data, statistics, and events.
The MCS persistence layer is responsible for early-commit write operations. When the software layer passes data to the persistence layer, the driver can immediately signal operation completion, even if the I/O has not entirely filtered through the FTL (Flash Translation Layer) to the NAND. EverGuard power-loss protection is the key to early-commit. Any data in the MCS Persistence Layer will be persisted to the media, even in the event of host power loss.
The internal block diagram of the ULLtraDIMM reveals device-based internal parallelism as well. The two flash controllers respond to data from the MCS controller, and handle each pool of NAND in an aggregated fashion.
Diablo and SanDisk aren't content to rest on their laurels. The MCS architecture is media agnostic and can work with future non-volatile memories such as 3D NAND, resistive NAND, Magentoresistive NAND, and phase change memory. The current implementation communicates via SCSI in Windows and VMWare, but the modular design can allow other protocols, such as NVMe, in the future.
Millions of DRAM products have shipped into the datacenter, but not one of them has actually stored one bit of data. Volatility is a major challenge, and Diablo and SanDisk are developing memory-mapped units that emulate main memory to provide a large in-memory processing pool. DRAM has a much higher cost structure than flash, not to mention power consumption, so the prospect of utilizing NAND with DRAM-like response times is alluring. In-memory processing is systematically backed-up or check-pointed, but a persistent memory layer lifts that requirement. DRAM is often used to accelerate I/O, and by alleviating that burden, it can be dedicated back to application processing.
The new Carbon2 architecture is currently in development. Carbon2 features DDR4 support, lower latency from a souped-up processing engine, and NanoCommit Technology. NanoCommit is an API that allows DRAM persistence at nanosecond latencies to NAND flash, and enables mirroring of DRAM to persistent storage.
MCS doesn't require any operating system or application modifications, but Diablo is working with several ISV's, including Percona and VMWare, to enhance interoperability. Partnerships with these leading vendors will provide enhanced performance in key applications, such as VSAN and database environments.
VSAN features both flash and spindle tiers for data storage. Each disk group has one flash drive, and up to seven spindles. A key advantage of the ULLtraDIMM is that multiple devices appear as one flash volume to the system. This allows for easy scaling of capacity and endurance in the flash tier; administrators can simply add more ULLtraDIMMs to address application performance, endurance, and capacity requirements. This desirable attribute avoids adding more drives to the spindle tier. Diablo provides in-depth VSAN performance comparisons against PCIe SSDs in their VSAN whitepaper.
Last updated: Nov 15, 2019 at 01:16 pm CST
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- Page 1 [Introduction]
- Page 2 [Internals and Specifications]
- Page 3 [MCS Management Console]
- Page 4 [MCS Architecture and VSAN]
- Page 5 [Guardian Technology Platform]
- Page 6 [Test System and Methodology]
- Page 7 [Benchmarks - 4k Random Read/Write]
- Page 8 [Benchmarks - 8k Random Read/Write]
- Page 9 [Benchmarks - 128k Sequential Read/Write]
- Page 10 [Database/OLTP and Webserver]
- Page 11 [Email Server]
- Page 12 [Final Thoughts]