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Intel Core i7 - Nehalem Arrives and FSB Departs (Page 2)

Cameron Johnson | Nov 1, 2008 at 11:00 pm CDT - 6 mins, 6 secs reading time for this page
Rating: 94%Manufacturer: Intel

Intel "Nehalem" Core i7 Architecture

Intel Core i7 Processor

Intel's latest addition to the Core architecture is the Core i7 series, which is based on the same architecture that made the Core 2 series so popular, but with a few major changes to the design.

Bye Bye FSB - Hello QPI

The first and foremost change is the removal of the FSB from the processor. Since the introduction of the processor, the CPU is connected to its Northbridge through the Front Side Bus. This is a communication bus that runs at a set MHz and is determined by the architecture used. This bus allows the CPU to send data to and from the system memory.

To replace the aging FSB, Intel has designed a new point-to-point communication protocol which is known as Quick Path Interconnect or QPI. Intel's first generation of QPI is a 20-bit interface with bi-directional communication running at either 4.8GT/s for the Core i7 range or 6.4GT/s for the Core i7 Extreme range of processors.

Integrated Memory Controller

This design had a major advantage, it allows for the CPU to be paired with different memory technologies. We have seen the Core 2 support DDR2 and then upgrade to DDR3 by changing the memory controller on the Northbridge. While it does allow an easy upgrade path, there is a major drawback, that being bandwidth restrictions. In order for the CPU to communicate with the memory, it first has to transmit a request through the FSB to the Northbridge. The Northbridge then needs to change that request into something the memory can understand; the request is then sent along the memory bus and onward to the modules.

Core i7 follows the example that AMD set out with the Athlon 64 processor and that is to move the memory controller on to the CPU die. The major advantage this brings is direct access for the CPU to the memory, allowing for a much higher bandwidth than possible using the FSB method. AMD proved this by having higher memory bandwidth using just 800MHz DDR2 memory, where Intel needed XMP 1600MHz to come close to AMDs memory performance.

While moving the memory controller on to the CPU package, Intel has decided to do the one up on AMD. Rather than just using dual channel memory, Intel has put a triple channel memory controller onto the CPU. With Core i7 we see Intel finally wave goodbye to DDR2 memory altogether. Core i7 supports only a single memory controller and the memory of choice is DDR3; so for those hoping Core i7 will support your older DDR2 modules, you're out of luck and will need DDR3 to get started.

Cache Increases

One of the ways that Intel has been increasing performance is by adding extra features, one of them is by increasing cache sizes. Core 2 saw quite a few different cache sizes, from 2MB all the way up to 6MB (12MB on quad cores with 2x6MB). Core i7 has been granted three levels of cache. Each of the four cores in the Core i7 gets 32K of L1 Data and 32K L1 Instruction cache; in total, 256KB of L1 cache. Next, rather than a shared L2 cache, each core gets 256KB L2 cache to itself, totalling up 1MB. Lastly, the CPU has a shared L3 cache to help increase overall performance; the cache size is 8MB shared amongst all four cores.

HT makes a comeback

Hyper Threading was Intel's first attempt at creating a Multi-Threading CPU. This was introduced on the Pentium 4 Northwood core series from 2.4GHz all the way to the end of the Pentium 4 series. While it was dropped on the Pentium D series, it made a return on the Pentium Extreme Edition, giving the CPU two cores with two logical units or four threads. HT has already made its appearance in the form of the Atom processor, allowing it to process two threads on a single core. Intel has seen fit to revive Hyper Threading on the desktop series by giving each of the four cores a HT system. So what we experience under Windows XP or Vista are eight cores; four physical and four threads.

New Instruction Set

SSE4 has been Intel's latest addition to their multimedia instruction sets. SSE4 was broken up into two different packages; SSE4.1 was introduced on the Penryn 45nm Core 2 series processors and consisted of 47 new instructions. SSE 4.2 is the latest addition and makes its debut on the Core i7. SSE4.2 consists of seven new instructions aimed at media acceleration.

New Platform, New Chipset

Intel Core i7 Processor

Because of the re-design of the Core i7, Intel has needed a new chipset in order to handle it. Keeping with the current naming system, Intel has for its chipsets the first generation of the 5 series making its debut with Core i7. X58 is a totally new design chipset from Intel. All of Intel's chipsets until now have had the memory controller as part of the chipset, which spawned the name Memory Controller Hub or MCH. The X58 chipset is the first from Intel to be naked of the memory controller; since it has been integrated to the CPU, there is simply no need for one on the X58.

X58 shares the same amount of PCI Express lanes as the X48 series, 36 in total. This allows for the system to be configured with either two PCIe x16 slots running off the Northbridge or configured in a 16/8/8 array for 3-way graphics. The X58 is paired with the ICH10 ICH so there is no new interface connecting the Northbridge to the Southbridge; it's simply using the same 2GB/s DMI that Intel has used since the ICH4. While we are on the subject of the PCIe configuration, X58 is the first chipset to come out with native support for SLI and Crossfire. Well, in theory; let's have a little background here first.

Over the last 3-4 months prior to launch, Intel has been desperately trying to get SLI certification for the X58 platform. NVIDIA told Intel that if they wanted to get SLI, the OEMs would have to install one or two of the nForce 200 PCI Express bridge chips. This caused quite an uproar amongst the motherboard manufacturers; not only is the NF200 chipset extremely expensive just to give SLI support, but it takes up quite a bit of real estate on the PCB just for one, let alone two. And the amount of energy one of these chips uses is higher than the X48 MCH alone. For these reasons, quite a few motherboard companies told NVIDIA in no uncertain terms that they would not be using their chipsets and they would have to work on another premise.

NVIDIA finally gave in and said that X58 boards will have to be submitted to NVIDIA for the validation of SLI. If it passes the tests, the company would be given a SBIOS code to install into all the BIOS' of that series of board, which would allow the NVIDIA ForceWare drivers to enable SLI on the X58 chipset. So unless it says it has SLI on the box, it won't support it, as it needs an SBIOS code rather than a driver hack. As for Crossfire support, AMDs open platform allows the X58 to simply plug in any Crossfire certified cards and run Crossfire in dual or quad GPU arrangements; whatever the user wants.

Last updated: Apr 7, 2020 at 12:27 pm CDT

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ABOUT THE AUTHOR - Cameron Johnson

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