CPU, APU & Chipsets News - Page 150

All the latest CPU and chipset news, with everything related to Intel and AMD processors & plenty more - Page 150.

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Intel Core i7-5960X Haswell-E CPU spotted in leaked photos

Anthony Garreffa | Aug 17, 2014 11:27 PM CDT

It shouldn't be long until Intel officially launches its new X99 chipset along with a slew of new high-end processors, with the star of the Haswell-E show being the upcoming Core i7-5960X processor. This new CPU has been spotted in some newly leaked photos that Hermitage Akihabara got its hands-on.

Intel's new LGA 2011-based Haswell-E processors are expected to be released on August 29, with three models to be unveiled: the Core i7-5960X, the Core i7-5930K and the Core i7-5820K. The top-of-the-line Core i7-5960X will have eight physical cores and eight provided through Hyper-Threading for a total of 16 threads - a monster of a consumer CPU.

The new Core i7-5960X will also feature 20MB of L3 cache, quad-channel DDR4 RAM support, and 40 PCIe 3.0 lanes in total. The default clock speed on the Extreme CPU will be 3GHz, and it'll be built on Intel's 22nm process.

Continue reading: Intel Core i7-5960X Haswell-E CPU spotted in leaked photos (full post)

NVIDIA's new Denver-based Tegra K1 is 64-bit, very powerful

Anthony Garreffa | Aug 11, 2014 11:29 PM CDT

NVIDIA's Tegra K1 processor is quite the performance powerhouse, with a quad-core processor with four A15 CPUs, up to 2.3GHz clock speed, and a 192 Kepler-based GPU cores for the graphics side of things. We've seen the Tegra K1 power NVIDIA's cheap, but very powerful Shield Tablet, but the company is already showing off the next version of its SoC.

At HOT CHIPS, a technical conference in the world of high-performance chips, NVIDIA has unveiled more details on the 64-bit version of its Tegra K1 processor. The 64-bit Tegra K1 is powered by the 192-core Kepler GPU, with NVIDIA's own custom-designed 64-bit, dual-core "Project Denver" CPU, which is fully ARMv8 architecture compatible. The big shift here is that the Denver part of the Tegra K1 is a dual-core variant, with a clock speed of up to 2.5GHz, but is 64-bit capable. The current Tegra K1 is a quad-core chip, with 32-bit capabilities. This makes the 64-bit Tegra K1 the world's first 64-bit ARM processor for Android, demolishing the competition when it comes to performance.

NVIDIA has used some clever optimizations, as well as its advanced technology in its Denver CPU cores, to deliver performance from its dual-core Denver-based Tegra K1 that rivals even four or eight-core CPUs that we find in our mobile devices today. Better yet, The 64-bit Tegra K1 processor offers PC-class performance, extended battery life, better gaming and multi-tasking, and much more. NVIDIA will see its 64-bit Denver-based Tegra K1 processor baked into mobile devices later this year, with the company also teasing that it is already working on support for the upcoming release of Android L on its 64-bit Tegra K1.

Continue reading: NVIDIA's new Denver-based Tegra K1 is 64-bit, very powerful (full post)

Intel has made no delays for its 10nm process technology

Roshan Ashraf Shaikh | Jul 17, 2014 5:26 AM CDT

Intel is facing troubles with its schedule of its 14nm manufacturing process, however the chipmaker said that this won't affect 10nm fabrication's schedule. Intel may be under the pressure to reassure its investors as its postponed its 14nm processor production plans that was supposed to roll out from its Fab 42 plant in Arizona, USA. 10nm is scheduled for mass-production for 2016.

Intel's CEO Brian Krzanich said during its quarterly conference call with financial analysts and investors,"We have done no changes or shift to our 10nm schedule, but we will not really talk about 10nm schedules until next year". However, Intel didn't reveal details about the production of these chips.

This might be the reason why Intel may show-off its first 10nm wafer during the upcoming Intel Developer Forum 2014. The demonstration of these wafers should reinvigorate investor's faith in Intel's schedule and in its tick-tock strategy, despite 14nm delays. It is also rumoured that Taiwan-based semi-conductor maker TSMC is also making plans to fabricate 10nm chips, which may also pressure Intel to go ahead of schedule with its 10nm roadmap.

Continue reading: Intel has made no delays for its 10nm process technology (full post)

Intel at IDF: 14nm CPUs and 10nm wafers to be shown off

Anthony Garreffa | Jul 13, 2014 5:01 AM CDT

It looks like things could get quite good at the Intel Developer Forum (IDF) in September, according to DigiTimes' sources. These sources have said that Intel will show off its 14nm processors in September, but it will also be teasing its 10nm wafers at the event, too.

DigiTimes' sources said: "Intel will release its 14nm Core M-series processors in the fourth quarter and 14nm Broadwell-based processors in January 2015". Intel is expected weaker-than-expected yields, and has a lot of 22nm-based processors in its inventory, and mixed with poor PC demand right now, Intel has reportedly "postponed 14nm processor production, which is planned to be conducted at its Fab 42 in Arizona, the US", according to these sources.

According to these sources, we should expect TSMC to pump up the mass production of its 20nm process in Q3 2014, where it will announce its 16nm FinFET process in 2015, followed by a 10nm process that will enter mass production in 2016.

Continue reading: Intel at IDF: 14nm CPUs and 10nm wafers to be shown off (full post)

AMD Carrizo APU rumoured to use 28nm process and stacked DRAM

Roshan Ashraf Shaikh | Jul 13, 2014 4:24 AM CDT

It seems that AMD is working on a new APU using 28nm process and stacked DRAM, codenamed 'Carrizo'. It is said that these APUs will benefit from HBM (Higher Bandwidth Memory) implementation compared to current DIMM slot counterparts.

Though the reports are unconfirmed, it is known that AMD is collaborating with Hynix to make stacked DRAMs. The HBM provides higher bandwidth which will benefitted by the APU especially by the onboard graphics core. The APU will be made with 28nm process, but the onboard HBM die will be based on 20nm process. Its speculated that Carrizo's APU core die size is smaller than Kaveri.

HBM can provide maximum bandwidth of 128-256GB/s, which will prove to be a better implementation over DDR4 support. These APUs will most likely use the FM2+ socket and maintains 65w TDP envelope. If AMD incorporates on package DRAM solution, it will allow higher speeds for the memory and have lesser latency even compared to DDR4 implementation and it would cost lesser than integrating L3 cache. Whether the stacked DRAM be implemented in all of Carrizo APU lineups and feasibility especially for low-cost APUs is currently unknown.

Continue reading: AMD Carrizo APU rumoured to use 28nm process and stacked DRAM (full post)

IBM spends $3 billion on new R&D, will step away from using silicon

Anthony Garreffa | Jul 11, 2014 12:30 AM CDT

IBM thinks that the days of silicon are numbered, as it spends $3 billion over the next five years on finding ways to create the future generations of microprocessors. Senior VP of IBM Systems & Technology Group, Tom Rosamilia, says: "We really do see the clock ticking on silicon".

Right now, IBM's very latest silicon components are baked onto a 22nm process, but the company is looking five years into the future where parts will become so small that it will be hard to maintain a reliable on and off state. Rosamilia adds: "As we get into the 7 nanometer timeframe, things really begin to taper off".

This has IBM looking at new ways of making components work, funding this new set of research. The company has faith in an alternative to silicon, something known as carbon nanotubes. The concept of this technology still needs considerable work if it hopes to see the fabrication of carbon nanotube-based processors as an alternative to silicon. Another route that IBM could go into is silicon nanophotonics, which uses light instead of electrical signals to blast data around the chip.

Continue reading: IBM spends $3 billion on new R&D, will step away from using silicon (full post)

TSMC invests heavily into 10nm process, wants to fight off Samsung

Anthony Garreffa | Jul 10, 2014 1:35 AM CDT

TSMC is reportedly increasing the development of its upcoming 10nm process so that it can better prepare itself against Samsung, which has reportedly received an order from Qualcomm to build 14nm FinFET chips, reports DigiTimes.

DigiTimes writes: "TSMC and Samsung are currently competing fiercely in the development of FinFET process, with the Korea-based foundry house utilizing a 14nm process and TSMC a 16nm node. Both the 14nm and 16nm processes are scheduled to enter volume production in early 2015". TSMC has been at the forefront of FinFET development, with plans to begin producing 16nm FinFET chips in Q4 2014.

DigiTimes' sources have said that TSMC has rescheduled its commercial production for the 16nm FinFET process, pushing forward with the more advanced 16nm FinFET Plus process. This process will consume less power, and shrink die sizes even more. TSMC is running scared at the moment, as it didn't anticipate Samsung to develop its 14nm process so quickly, so now the Taiwanese company is accelerating its development of the 10nm process, to continue staying out ahead of its competitors.

Continue reading: TSMC invests heavily into 10nm process, wants to fight off Samsung (full post)

VIA could jump back into the CPU game with its next-gen Isaiah chip

Anthony Garreffa | Jul 9, 2014 4:34 AM CDT

If new reports are to be believed, VIA is working on the next-generation version of its x86-based CPU architecture, Isaiah. The company's last try at the x86 CPU game was back in 2006, but the latest version looks like it'll be released in just a few weeks time.

German site 3DCenter is reporting on some of the performance comparisons with other low-power chips, such as AMD's Kabini APU which has a 25W TDP, and a mobile Bay Trail processor from Intel. Isaiah II looks like it can keep its own, but we don't know how genuine these benchmarks are, if they are genuine at all. Centaur is the name of VIA's CPU division, with its website teasing an upcoming refresh which will happen on September 1. This could be the date when we learn about the new CPU, so we'll be keeping our eyes open.

We can also confirm hearing stories from certain VIA employees at Computex that its next-gen CPU may end up being able to compete with Intel Core i5 level parts at low power consuming levels.

Continue reading: VIA could jump back into the CPU game with its next-gen Isaiah chip (full post)

Russia to use local CPUs in its government PCs, ditches US-made chips

Anthony Garreffa | Jun 24, 2014 5:53 AM CDT

The Russian Industry and Trade Ministry has announced plans to replace the US-made processors from companies like Intel and AMD, with its own x86-based processors. These new processors will run on a new Linux-based system, with a CPU built-in Russia called Baikal.

Baikal is being made by an electronics division of T-Platforms, a supercomputer maker, and looks to have some serious funding being pumped into it. Rosnano, a technology firm, and Rostec, a rather large defense contractor, are both chipping into the project. The first processors off the production line will feature an ARM Cortex A-57 at 2GHz, and will run both PCs and servers.

Each and every year, the Russian government reportedly purchases 700,000 PCs which costs around $500 million. On top of this, the government spends a further $300 million acquiring 300,000 servers per year. The new Baikal processors should begin replacing the Intel- and AMD-powered machines starting in early 2015.

Continue reading: Russia to use local CPUs in its government PCs, ditches US-made chips (full post)

Experimental 36-core CPU teased, with each core featuring a router

Anthony Garreffa | Jun 24, 2014 5:29 AM CDT

Intel is about to launch its 16-threaded (but 8-core) processor in September, and while that is for consumers, what is being played with behind closed doors in experiments is incredibly exciting - with a new 36-core processor teased by researchers at the International Symposium on Computer Architecture.

Li-Shiuan Peh, the Singapore Research Professor of Electrical Engineering and Computer Science at MIT, has said that the future of massively multi-core processors will be more like little Internets, where every core packs a router, with data travelling between cores in packets of fixed size. Peh's group unveiled a titanic 36-core processor that features this "network-on-chip" at the event.

Today's processors are connected by a single wire, and feature between 2 and 6 cores, with the multiple cores needing to talk to each other through exclusive access to the bus. But, this way won't work as the core count increases, as the other cores will be waiting for the bus to free up, rather than performing the duties you've set it out to do. With the network-on-chip, each and every CPU core is connected only to those that are directly next to it. Bhavya Daya, an MIT graduate student in electrical engineering and computer science explains: "You can reach your neighbors really quickly. You can also have multiple paths to your destination. So if you're going way across, rather than having one congested path, you could have multiple ones".

Continue reading: Experimental 36-core CPU teased, with each core featuring a router (full post)