SK hynix has 'high hopes' for its advanced packaging plant in the US

SK hynix wants utter world domination in the HBM and advanced packaging markets, with its new Arizona, USA-based plant gearing up for all-systems-go in the coming years on US soil.

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In an interview posted on SK hynix's own blog last week, the vice president in charge of SK hynix's package and test division, Choi Woo-jin, said: "Package and test (P&T) technology is turning into a crucial factor in the battle for semiconductor leadership".

Choi is a packaging expert who has conducted and led research and development in chip memory packaging over the last 30 years, with the P&T division at SK hynix that he runs taking care of the back-end process where wafers are packaged into products and tested, ensuring their meet the strenuous demands of customers.

The world of semiconductor packaging is one of the most important parts of HBM and is a critical part of AI GPUs. Packaging is traditionally used to electrically connect chips to protect them from external shocks; Choi stressed that packaging technology is vital to enabling differentiated product performances. He said: "In the age of AI, SK hynix is focusing on signature memories which possess diverse aspects required by customers, including various capabilities, sizes, shapes and power efficiency".

• Read more: SK hynix confirms $3.87 billion advanced packaging plant, R&D facility for Indiana, USA

It wasn't just now, but the future that Choi talked about: with the SK hynix VP highlighting the company's quick response to the insatiable demand of AI GPUs and their required DRAM (HBM3, HBM3E, HBM4, etc). This meant quickly adopting through-silicon via (TSV) packaging lines to boost production capacity without spending more money.

SK hynix notes that by advancing its proprietary technologies, including TSV and mass reflow-molded underfill (MR-MUF), the South Korean company has enhanced its HBM performance. Choi also teased that SK hynix is working on multiple next-generation packaging technologies, including chiplet4 and hybrid bonding.

TSV can reduce the thickness of a single DRAM chip by up to 40% and hit the same stack height level as the 16-gigabyte product. MR-MUF technology can place multiple chips on teh lower substrate and bond them at once through reflow, and then simultaneously fill teh gap between teh chips with a mold material.

Choi added: "Once the factory is fully operational, we expect it to make a significant contribution to strengthening the company's AI memory technology and business leadership. In the short term, we plan to strengthen our domestic production capabilities to meet the demand for HBM while leveraging our global base to maximize profitability. In the long run, we aim to secure more innovative packaging technologies like MR-MUF, which is now a vital technology to HBM".