PCIe 6.0 connectivity demoed at NVIDIA GTC 2024: ready for Blackwell B100, B200, GB200 AI GPUs

Astera Labs was demoing its working PCIe 6.0 connectivity with next-gen Aries PCIe 6.0 retimers, spotted on the NVIDIA GTC 2024 showfloor by our friends at Tom's Hardware. Check it out:

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We don't even have PCIe 5.0 across the board with all PC users and gamers, but PCIe 6.0 is coming with NVIDIA's new Blackwell B100, B200, and GB200 AI GPUs all ready for Gen6. AI workloads require ridiculous amount of throughput through the GPUs to process everything at full speed, with NVIDIA using its in-house custom NVLink and NVSwitch to offer massive GPU-to-GPU communication, offering up to 1.8TB/sec of bandwidth on GB200-powered systems.

Not every customer wants the entire NVIDIA solution, which is where PCIe 5.0 x16 connections step in for the current fleet of AI GPUs, but Blackwell introduces PCIe 6.0, doubling the 128GB/sec of bandwidth of an x16 connection on PCIe 5.0 to a huge 256GB/sec bandwidth on PCIe 6.0 x16.

• Read more: PCIe 6.0 spec detailed: next-gen PCIe 6.0 SSDs up to 64GB/sec reads
• Read more: NVIDIA rumored to mandate PCIe 6.0 16-pin connector for RTX 50 GPUs
• Read more: PCI-SIG announces new naming scheme for PCIe cables: CopprLink

Tom's Hardware spotted Astera Labs' new Aries Smart DSP retimers at NVIDIA GTC 2024, with the small chips boosting the PCIe 6.2 signal. The demo systems had boards running an active PCIe 6.2 link between the host on the left system, and the load generator on the right. Aries PCIe 6.0 retimers are found on the interposer board in the middle, ingesting and boosting the traffic between its dual PCIe 6.0 x16 connectors (one on each side of the retimer itself).

Astera Labs had live power measurements of its new PCIe 6.0 retimer chip, which they're proud to say is the world's lowest-power retimer. Under full load, the chip had 11W of power draw, which is around 15% less than the 13W that is consumed under full load on PCIe 5.0, while pumping twice the bandwidth through it.

The new PCIe 6.0 retimer silicon is on a newer TSMC process node (the company didn't state which node exactly), which helps with the power savings of its Astera Labs' new chip. Astera Labs' new PCIe 6.0 retimer will be used on a wide range of PCIe 6.0-powered devices, including GPUs, SSDs, NICs, and more, but they're all under NDA so we don't know anything about them just yet.

Astera Labs' new PCIe 6.0 retimer (source: Tom's Hardware)

PCIe 6.0 doubles the available bandwidth on an x16 connection to 256GB/sec, up from 128GB/sec, with the increase delivered from a switch to PAM-4 encoding instead of NRZ, with no frequency increase, so the reach/distance requirements are about the same. PAM-4 encoding is more susceptible to errors, so error rates have bumped even though the addition of forward error correction (FEC).

Bandwidth has doubled, and error rates have increased, which reduces the effective bandwidth. High-end retimers can ensure signal integrity, with Astera Labs' customers either designing systems with longer trace lengths and accepting the error rates, or they can use short trace lengths to reduce error rates but boost bandwidth in the process.

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Astera Labs' already has a big customer with NVIDIA, with their retimers powering NVIDIA DGX HPU systems. The company had a current HGX system with 8 x NVIDIA H100 AI GPUs in the OAM form factor, placed on a universal baseboard (UBB, an OCP spec design).

With the insatiable AI demand worldwide right now, these systems are in a shortage, with Astera Labs must be loving as they're providing NVIDIA with retimers for these AI systems.