AMD introduces SSE5 x86 instruction set

Will show up on Fusion.

| Aug 30, 2007 at 9:40 pm CDT
AMD has always struggled to keep up with instruction sets on their CPUs in line of what Intel are including at the time. As an example, it took AMD nearly three years to add SSE3 to their latest CPUs at the time (first crop of Athlon 64s) following Intel's Pentium 4 launch.

However! - It appears AMD are really trying their hardest to make up for lost ground with an announcement from them today that they are working on an all-new instruction set which not even Intel have mentioned anything about yet.

Though SSE5 instructions are available to developers now, we wont see them included into products until the next-gen Fusion architecture with Bulldozer CPU cores, this supposedly some time in 2009.

According to AMD's press release, SSE5 will bring the following advantages :-

* 3-Operand Instructions A computing instruction is executed by applying a mathematical or logical function to operands, or inputs. By increasing the number of operands an x86 instruction can handle from 2 to 3, SSE5 enables the consolidation of multiple, simple instructions into a single, more effective instruction. The ability to execute 3-Operand Instructions is currently only possible on certain RISC architectures.

*Fused Multiply Accumulate The 3-Operand Instruction capability enables the creation of new instructions which efficiently execute complex calculations. The Fused Multiply Accumulate instruction combines multiplication and addition to enable iterative calculations with one instruction. The simplification of the code enables rapid execution for more realistic graphics shading, rapid photographic rendering, spatialized audio, complex vector mathematics and other performance-intense applications.

AMD go on to say that SSE5 helps maximize the output of each instruction and consolidates code base by introducing functionality previously only found in specialized, high-performance architectures, to the x86 platform."

The official announcement from AMD can be read here, and there's more info about SSE5 to be found at this page on AMD's Developer Central site.

Furthermore, the lads over at Anandtech have shared their first thoughts with us all about SSE5 here.

SUNNYVALE, Calif -- August 30, 2007 --AMD today announced further plans to innovate the x86 architecture by introducing SSE5, a new extension of the x86 instruction set that is designed to allow software developers to simplify code and achieve greater efficiency for the most performance-hungry applications. SSE5 will give developers additional capabilities to help maximize the performance of applications that have daily impact on consumers and enterprises, including high performance computing, multimedia and security applications. By making the SSE5 specification available to developers today, AMD expects to ease the adoption of the new instructions for tool providers and software vendors who develop these performance-intense applications.

Last updated: Jun 16, 2020 at 04:29 pm CDT


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