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Intel Core 2 Duo is here - could it be Intel's day to shine?

By: Cameron Johnson | Intel CPUs in CPUs, Chipsets & SoCs | Posted: Jul 14, 2006 4:00 am

Core Architecture in detail


The Core Architecture is now a step away from Intel's future proof Netburst architecture in quite a few ways. In fast it's almost totally redesigned, only using the same FSB and electrical connections to make it compatible with Socket 775 and existing Pentium 4 supporting chipsets like the Intel 975X, this is where things end in similarities.


Intel's Core Architecture includes a few new technologies that distinguish it from the previous generation CPU. Multi Platform Architecture, Wide Dynamic Execution, Intelligent Power Capability, Advanced Smart Cache, Smart Memory Access and Advanced Digital Media Boost to name just a few. So let's have a look at a few of these features and try to explain them as best as possible without needing a degree in rocket science.


- Multi Platform Architecture


Intel's Core Architecture is a first for Intel's platform development. Core Architecture has been designed to support not only the desktop environment but also mobile and servers. With different array of power saving features, cache sizes and bus implementations, core based CPU's can be tailored for each platform. Benefits of this style of architecture means there is no added costs in researching a separate CPU platform architecture to run servers, desktops and notebooks, using a single architecture that can be tailored during production allows a cheaper CPU and platform cost to the consumer.


- Intel Wide Dynamic Execution


Wide Dynamic Execution is just a fancy way for Intel to say it has widened the execution path of core CPU's. Rather than 3 execution pipes, core CPU's have 4. This allows the Core Architecture to process 4 simultaneous instructions per clock cycle. This reduces the amount of clock cycles needed to execute a program, reducing power consumption as the CPU is at load for less time. With Wide Dynamic Execution comes another feature built into the pipeline called "Macro Fusion". When the instructions are loaded into the decoder, if a common pair of instructions are found in the decode buffer, Macro combines the 2 and sends them down to the Execution stage in a single packet. This doubles the data that is sent allowing 2 instructions to be sent simultaneously. Increasing the amount of data processed per clock cycle.


- Intel Intelligent Power Gating


Intelligent Power Gating is further work by Intel on its SpeedStep technologies, only taken up a notch. When the CPU isn't required to run at 100% load, previous CPU's like the Pentium 4 and even the AMD Athlon 64 still turn on the full amount of execution pipes and so on. Intelligent Power Gating determines how much CPU resources are needed and only turns on what is needed and leaves the rest in an idle state. This allows certain areas of the CPU to remain idle while others are operating. If more are needed, the CPU will open up the extra gates and bring the CPU up out of idle state without the user noticing any performance hit. This technology is especially useful for the mobile sector allowing for a greater battery life as well as desktop and small form factor PC's reducing the amount of power and heat generated per clock cycle.


- Smart Cache Technology


Smart Cache is Intel's latest way of not only reducing the amount of cache memory needed for its dual core CPU's but also a way to increase the efficiency of the data being shared between the 2 cores. Traditionally in dual core CPU's you have 2 separate CPU's with their own L1 and L2 caches fused together on a single die and using either the FSB for core to core communication like in the Pentium D or Pentium Extreme Edition CPU's from Intel or a Crossbar interface such as the AMD Athlon 64 X2's. Smart Cache works differently in that both cores have a separate L1 cache but share a common L2 cache.


This cache is dynamic allocation and power saving. Dynamic allocation means that which ever core needs the most amount of L2 cache, then that core gets the most amount. If both need the same amount, the cache is split down the middle for each core. This also reduces latency between core to core communication as both cores can access the same data in L2 cache at the same time allowing each core to know what each other is doing rather than having to come across the FSB and into main memory like the previous Pentium D/XE range of CPU. This also reduces cache misses in that if core 1 requires some data from the L2 cache it is loaded into the common cache, in traditional dual core, this data may be in core 2's L2 cache, resulting in a cache miss and requiring the L2 cache of core 1 to access the data from main memory while core 2's L2 cache needs to be cleared of this data.


The power saving feature is derived from the Pentium-M series CPU. When the CPU enters the idle state, half of the cache is dynamically turned off and put into a deep state of hibernation until it is needed, further reducing the amount of power consumed by the CPU when under idle states.


- Smart Memory Access


Intel's Smart Memory Access includes a new technology called memory disambiguation. With this new feature each core is able to guess what data is needed from memory and is able to retrieve it before all the previous instructions in the queue have been completed. This allows for reduced memory latency as well as a much simpler memory allocation system. Should the data received be the wrong packet, the instruction is sent back to the execution engine to await the right data, which prevents stalls and wait states.


- Digital Media Boots


This is by far one of the more interesting features of the Core Architecture. Streaming SIMD instructions are 128-bit codes put together in packages, for Intel they are SSE, SSE2 and SSE3. Previous CPU's to execute these had to be broken down into 64-bit instructions, so for a Netburst based CPU to execute a single SIMD Instruction it would take 2 clock cycles, 1 cycle to execute the top 64-bits and a second cycle for the lower 64-bit. With the new deeper execution buffers in the new Core architecture CPU's, the execution engine can process a single 128-bit instruction in just 1 clock cycle. This is particularly useful when graphical media and content creation is involved as well as encoding of audio and video media.

Intel Core™ Duo T2600, 2.16 GHz Core Duo (BX80539T2600) Intel Boxed Processor


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