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AMD launches Mobile Ryzen with Radeon Vega Graphics

By: Steven Bassiri | AMD CPUs in CPUs, Chipsets & SoCs | Posted: Oct 26, 2017 1:00 pm

Internal Power Optimizations

 

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One way to extend battery life is to increase battery size or density, but since people don't like to lug around ten-pound bricks, vendors increasing want lower power processors. AMD has gone ahead, and optimized power consumption on the new processors and they have aimed for a 2X improvement in battery life. We see a 2X improvement with VP9 playback (like YouTube) compared to the previous generation.

 

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AMD has gone ahead and produced a CPU that only requires a single input, much like Intel's FIVR, but with linear regulators. A single VDD (like VCore or VCC, stands for Voltage Drain to Drain) output goes to internal regulators that then provide different domains with different voltage and current levels. The onboard voltage regulator utilizes digital LDO. While we are talking about big regions here such as the CCX or Vega, there are also many sub-regions as well that can be power gated for a max current reduction of 36%.

 

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AMD has also included per-core frequency and voltage control. The new systems will move power where it is needed and doesn't threat all cores equally. We can see that this per core frequency and voltage control works to optimize power efficiency based on core-to-core and CPU-to-GPU utilization. That means that when the GPU is high in demand, the CPU cores will give up some power to the GPU and then they will take it back when required, on a case by case basis for each core.

 

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Power savings modes are also extremely important for a mobile CPU, as is the ability to come back from a sleeping state. Each core can enter CC6 (C0 is awake) on its own, and the CPU and GPU and be turned off. The integrated linear regulators are to thank for this capability, and 95% of the GPU can be powered down or even 100%. It doesn't stop there though, AMD added a dual region approach to power gating in the Infinity Fabric. Communications between different regions in a SoC can be power intensive, but AMD has found a way to basically disable one part while leaving another open. An example is a display refresh, and during the refresh, not all blocks need to communicate, so only one key set is enabled allowing all that should communicate to communicate while shutting down communications between others that don't need to be on.

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