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533FSB Pentium 4 Chipset Shootout - Intel -vs- SiS -vs- VIA

By: Cameron Johnson | Intel CPUs in CPUs, Chipsets & SoCs | Posted: Sep 13, 2002 4:00 am


SiS645DX - An Intel Alternative


The SiS645DX Host Interface features the AGTL & AGTL+ compliant bus driver technology with integrated on-die termination to support Intel Pentium 4 series processors. It provides a 12-level In-Order-Queue to support maximum outstanding transactions on the host bus up to 12. The host interface plays the role of processor transactions dispatcher. It dispatches transactions to Memory, I/O interface and AGP bus. Transactions to different destinations can be dispatched concurrently in order to maximize pipeline efficiency. In addition to dispatching the processor's transactions to corresponding destinations, host interface also forwards DMA transactions from AGP masters and I/O masters to the host bus for snooping, including master interrupt delivery.


The memory controller can support both DDR and SDR. It can offer bandwidth up to 2.7GB/s under DDR333 and 1GB/s under PC133 in order to sustain the bandwidth demand from host processor, as well as the multi I/O masters and AGP masters. The Memory Controller mainly comprises the Memory Arbiter, the M-data/M-Command Queues, and the Memory Interface. The Memory Arbiter arbitrates a plenty of memory access Host Controller, and I/O bus masters based on a default optimized priority list with the capability of dynamically prioritizing the I/O bus master requests in a bid to offering privileged service to 1) the isochronous downstream transfer to guarantee the minimum latency & timely delivery, or 2) the PCI master upstream transfer to curb the latency within the maximum tolerant period of 10us. Prior to the memory access requests pushed into the M-data queue, any command compliant to the paging mechanism is generated and pushed into the M-CMD queue. The M-data/M-CMD Queues further orders and forwards these queuing requests to the Memory Interface in an effort to utilize the memory bandwidth to its utmost by scheduling the command requests in the background when the data requests streamlines in the foreground. The memory controller also supports the Suspend to RAM function by retaining the CKE# pins asserted in ACPI S3 state in which only AUX source deliver power.


The AGP interface can support an external AGP slot with AGP 1X/2X/4X capability and Fast Write Transactions. A high bandwidth and mature SiS MuTIOL technology is incorporated to connect SiS645DX and SiS961 MuTIOL Media I/O together. SiS MuTIOL technology is developed into three layers, the Multi-threaded I/O Link Channels Layer delivering 1.2GB bandwidth to connect embedded DMA Master devices and external PCI masters to interface to Multi-threaded I/O Link Packet layer, the Multi-threaded I/O Link Packet Layer in SiS961 to transfer data w/ 533 MB/s bandwidth from/to Multi-threaded I/O Link Channels layer to/from SiS645DX, and the Multi-threaded I/O Link Packet Layer in SiS645DX to transfer data w/ 533 MB/s from/to memory sub-system to/from the Multi-threaded I/O Link Packet Layer in SiS961(B).


The SiS 645DX is a full fledged effort by SiS to gain market shares. With licensing disputes between VIA and Intel, the SiS 645DX is the only official DDR-333 licensed P4 chipset available. Tier 1 motherboard vendors are not putting their faith in the unlicensed VIA solutions and are sticking more towards Intel i845 and SiS products.


Below is an architectural diagram of the SiS 645DX chipset for your reference.



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