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Micron P420m 1.4TB PCIe Enterprise SSD Review - P420m Architecture and XPERT Suite

Micron P420m 1.4TB PCIe Enterprise SSD Review
Micron's P420m utilizes 25nm MLC NAND to deliver a competitive product for mainstream enterprise storage usage. Let's take a close look at it now. (NASDAQ:MU)
By: | PCIe SSDs in IT/Datacenter | Posted: Sep 13, 2013 9:16 pm
TweakTown Rating: 92%Manufacturer: Micron

P420m Architecture




The P420m does not employ bridging chips or hardware, providing an efficient contention-free architecture. The architecture combines all 64 placements of NAND into 32 ONFI 2.1-compliant channels, with no intermediary SSD controllers or RAID controllers. Several PCIe solutions feature multiple SSD controllers onboard the PCB, and these in turn feed a RAID controller. Micron simplifies the design, minimizing the amount of hardware, thus maximizing throughput and minimizing latency to the controller.


The Micron-developed ASIC controller provides an embedded ATA host bus adapter, a host/flash translation later, flash maintenance, channel control, and a NAND RAID (RAIN) protection scheme. This streamlined architecture also dispels clunky non-native interfaces, which tend to become the slow point in many solutions. Translating protocols from SAS or SATA to PCIe tends to incur latency penalties that are not a factor with the P420m, which enjoys native PCIe technology.


The Micron/IDT 89HF3208 controller is a 1517 pin FCBGA (Flip Chip Ball Grid Array) which handles 32 channels, supporting four-way interleaving up to 128 NAND die. The functions of the SSD are all handled on-die to minimize host overhead. The P320h features the same controller, making this a time-proven ASIC in long-term deployments.





The P420m is the first PCIe SSD to utilize Micron's XPERT suite to enhance the lifespan and data integrity of the drive. XPERT (eXtended Performance and Enhanced Reliability Technology) provides enhanced defect and error management technology.


This approach utilizes a combination of hardware based error correction algorithms, along with firmware-based static and dynamic wear-leveling algorithms.





Micron has taken error correction and avoidance to the next level with RAIN (Redundant Array of Independent NAND), which calculates and stores parity. This is in essence a RAID 5 implementation at the device level, storing one page of parity per seven pages of data, providing the ability to recover data in the event of an error or failure. RAIN provides data security beyond the standard ECC approach and recovers lost data beyond page, block and die-level failures.


This transparent process takes place without any degradation of the SSDs performance, but does come at the expense of capacity. This implementation relies upon extra NAND to store the data, but Micron has compensated for this with 28% overprovisioning on the P420m.



Data Path Protection


Data Path Protection ensures data integrity during transfer through the drive interface, DRAM, error checkers, data concatenations, and the retirement of NAND. This is accomplished through CRC and ECC algorithms before and after each element in the data path.

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