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Asus P4S8X SiS 648 Motherboard Review - Chipset Overview

Asus has long made motherboards with the enthusiast in mind. No matter the chipset or processor being supported, they have been there. Come join Tio Chaharbaghi as he delves into one of their latest offerings; the Asus P4S8X Motherboard. Using the new SiS 648 chipset, we will look at a number of areas to see if this newcomer can stand up to the Asus reputation. Come find out!

| Editorials in Motherboards | Posted: Oct 18, 2002 4:00 am
TweakTown Rating: 7.5%Manufacturer: Asus

Chipset overview

 

SiS648 HMAC The SiS648 Host & Memory & AGP Controller integrates a high performance host interface for Intel Pentium 4 processor, a high performance memory controller, a AGP interface, and SiS MuTIOL 1G Technology connecting w/ SiS963 MuTIOL 1G Media IO.

 

The SiS648 Host Interface features the AGTL & AGTL+ compliant bus driver technology with integrated on-die termination to support Intel Pentium 4 series processors with FSB 400MHz/533MHz. It provides a 12-level In-Order-Queue to support maximum outstanding transactions on host bus up to 12. The host interface plays the role of processor transactions' dispatcher. It dispatches transactions to Memory, I/O interface and AGP bus. Transactions to different destinations can be dispatched concurrently in order to maximum pipeline efficiency. In addition to dispatching processor's transactions to corresponding destinations, host interface also forward DMA transactions from AGP masters and I/O masters to host bus for snooping, including master interrupt delivery.

 

The memory controller supports DDR only. It can offer bandwidth up to 2.7GB/s under DDR333 in order to sustain the bandwidth demand from host processor, as well as the multi I/O masters and AGP masters. The Memory Controller mainly comprises the Memory Arbiter, the M-data/M-Command Queues, and the Memory Interface. The Memory Arbiter arbitrates a plenty of memory access Host Controller, and I/O bus masters based on a default optimized priority list with the capability of dynamically prioritizing the I/O bus master requests in a bid to offering privileged service to 1) the isochronous downstream transfer to guarantee the min. latency & timely delivery, or 2) the PCI master upstream transfer to curb the latency within the maximum tolerant period of 10us. Prior to the memory access requests pushed into the M-data queue, any command compliant to the paging mechanism is generated and pushed into the M-CMD queue. The M-data/M-CMD Queues further orders and forwards these queuing requests to the Memory Interface in an effort to utilizing the memory bandwidth to its utmost by scheduling the command requests in the background when the data requests streamlines in the foreground. The memory controller also supports the Suspend to RAM function by retaining the CKE# pins asserted in ACPI S3 state in which only AUX source deliver power.

 

The AGP interface can support external AGP slot with AGP 4X/8X capability and Fast Write Transactions. A high bandwidth and mature SiS MuTIOL 1G technology is incorporated to connect SiS648 and SiS963 MuTIOL 1G Media I/O together. SiS MuTIOL 1G technology is developed into three layers, the Multi-threaded I/O Link Layer delivering 1.2GB bandwidth to connect embedded DMA Master devices and external PCI masters to interface to Multi-threaded I/O Link layer, the Multi-threaded I/O Packet Layer in SiS963 to transfer data w/ 1 GB/s bandwidth from/to Multi-threaded I/O Link layer to/from SiS648, and the Multi-threaded I/O Packet Layer in SiS648 to transfer data w/ 1 GB/s from/to Multi-threaded I/O Link layer to/from SiS963.

 

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